Research Article
Design and Implementation of 4-bit High Speed Array Multiplier for Image Coding
@INPROCEEDINGS{10.1007/978-3-031-35078-8_32, author={Pramod Kumar Aylapogu and Kalivaraprasad Badita and P. Geetha and Namratha Sama}, title={Design and Implementation of 4-bit High Speed Array Multiplier for Image Coding}, proceedings={Intelligent Systems and Machine Learning. First EAI International Conference, ICISML 2022, Hyderabad, India, December 16-17, 2022, Proceedings, Part I}, proceedings_a={ICISML}, year={2023}, month={7}, keywords={Critical Latency Array Multiplier Propagation Latency Power Area Speed}, doi={10.1007/978-3-031-35078-8_32} }- Pramod Kumar Aylapogu
Kalivaraprasad Badita
P. Geetha
Namratha Sama
Year: 2023
Design and Implementation of 4-bit High Speed Array Multiplier for Image Coding
ICISML
Springer
DOI: 10.1007/978-3-031-35078-8_32
Abstract
Multipliers are the utmost commonly used elements in today’s digital electronics. In digital signal processing systems, hardware multiplication is critical for obtaining high data throughput. Based on the increasing applications of electronic devices, various types of multipliers have emerged. Array Multiplier is the most fundamental multiplier of all. The main goal of our project is to create an optimized and fast 4-bit array multiplier. Parallel Array Multipliers are used in DSP applications to do multiplication at high speeds while meeting performance criteria. The simulations are run on the Xilinx 14.7 ISE Design Suite.
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