Research Article
A Comparative Study of Power Optimization Using Leakage Reduction Techniques
@INPROCEEDINGS{10.1007/978-3-031-35078-8_31, author={Pramod Kumar Aylapogu and A. Jayalakshmi and Hirald Dwaraka Praveena and B. Kalivaraprasad}, title={A Comparative Study of Power Optimization Using Leakage Reduction Techniques}, proceedings={Intelligent Systems and Machine Learning. First EAI International Conference, ICISML 2022, Hyderabad, India, December 16-17, 2022, Proceedings, Part I}, proceedings_a={ICISML}, year={2023}, month={7}, keywords={Full adder SC-CMOS Sleepy Keeper Leakage Power}, doi={10.1007/978-3-031-35078-8_31} }- Pramod Kumar Aylapogu
A. Jayalakshmi
Hirald Dwaraka Praveena
B. Kalivaraprasad
Year: 2023
A Comparative Study of Power Optimization Using Leakage Reduction Techniques
ICISML
Springer
DOI: 10.1007/978-3-031-35078-8_31
Abstract
Designers have scaled down feature sizes, decreasing threshold voltage and allowing the integration of on a single chip, the functionality is becoming increasingly sophisticated. Due to the rapid improvement of semiconductor technology and the growing need for battery-powered portable electronics. To increase the number of devices in a concert, three critical factors are required: system speed, small space, and low power consumption. The entire power consumption of integrated devices is determined by leakage current dissipation in particular. In order to minimize power consumption, the leakage current must be lowered. This study article examines and analyses numerous leakage power reduction techniques, including SC-CMOS and Sleepy keeper. Inverter and Full adder reduction approaches are evaluated in terms of static and dynamic power. In this work, a new strategy for reducing leakage power in 90nm technology is suggested. The suggested approaches will be compared to other leakage reduction strategies that have been used in the past.
