Research Article
Comparison of Advanced Encryption Standard Variants Targeted at FPGA Architectures
@INPROCEEDINGS{10.1007/978-3-031-35078-8_29, author={Nithin Shyam Soundararajan and K. Paldurai}, title={Comparison of Advanced Encryption Standard Variants Targeted at FPGA Architectures}, proceedings={Intelligent Systems and Machine Learning. First EAI International Conference, ICISML 2022, Hyderabad, India, December 16-17, 2022, Proceedings, Part I}, proceedings_a={ICISML}, year={2023}, month={7}, keywords={AES Encryption FPGA Hardware Implementation}, doi={10.1007/978-3-031-35078-8_29} }- Nithin Shyam Soundararajan
K. Paldurai
Year: 2023
Comparison of Advanced Encryption Standard Variants Targeted at FPGA Architectures
ICISML
Springer
DOI: 10.1007/978-3-031-35078-8_29
Abstract
Digital communication of any form must provide data confidentiality as the threats are increasing in today’s rapid world. Data privacy and security are crucial factors as data is considered gold in the modern era. The 128-bit Advanced Encryption Standard algorithm, commonly known as AES, has been implemented in several designs, focusing on specific purposes and is used widely. The 256-bit variant uses the same fundamental cipher blocks as the 128-bit version but differs in key size, the key expansion function and the number of cipher rounds. This paper investigates the 256-bit AES algorithm targeted at FPGA-Field Programmable Gate Arrays architectures and compares it with the 128-bit implementation, reporting performance and resource utilization. Also, the security offered is discussed. The security is determined by the complexity of recovering the key using cryptanalytic attacks. Both encryption and decryption processes are handled by this implementation and are tested in Verilog language using the Xilinx Vivado software on the Xilinx Zynq-7000 (xc7z020-clg484-1) FPGA.
