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Blockchain Technology and Emerging Technologies. Second EAI International Conference, BlockTEA 2022, Virtual Event, November 21-22, 2022, Proceedings

Research Article

A Novel Fast Recovery Method for HT Tamper in Embedded Processor

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BibTeX Plain Text
  • @INPROCEEDINGS{10.1007/978-3-031-31420-9_8,
        author={Wanting Zhou and Shiwei Yuan and Lei Li and Kuo-Hui Yeh},
        title={A Novel Fast Recovery Method for HT Tamper in Embedded Processor},
        proceedings={Blockchain Technology and Emerging Technologies. Second EAI International Conference, BlockTEA 2022, Virtual Event, November 21-22, 2022, Proceedings},
        proceedings_a={BLOCKTEA},
        year={2023},
        month={4},
        keywords={hardware security GPRs fault recovery embedded processor},
        doi={10.1007/978-3-031-31420-9_8}
    }
    
  • Wanting Zhou
    Shiwei Yuan
    Lei Li
    Kuo-Hui Yeh
    Year: 2023
    A Novel Fast Recovery Method for HT Tamper in Embedded Processor
    BLOCKTEA
    Springer
    DOI: 10.1007/978-3-031-31420-9_8
Wanting Zhou1,*, Shiwei Yuan1, Lei Li1, Kuo-Hui Yeh2
  • 1: Research Institute of Electronic Science and Technology, University of Electronic Science and Technology of China, Chengdu
  • 2: Department of Information Management, National Dong Hwa University
*Contact email: zhouwt@uestc.edu.cn

Abstract

Nowadays, embedded processors face various hardware security issues such as hardware trojans (HT) and code tamper attacks. In this paper, a novel cycle-level recovery method for HT tamper in embedded processor is proposed, which consists two units, a General-Purpose Register (GPRs) backup unit and a PC rollback unit. The former one is designed to replace original register files with backup function extra. And the latter one is composed for rollback operations based on the exact PC address corresponding to the wrong instruction. If a HT tamper is detected, the backup unit works in conjunction with PC rollback unit allowing the processor to resume the instruction execution. The proposed method has been implanted into a RISC-V core of PULpino, and the experimental results show that the processor can restore from fault state caused by inserted HT in real time with the latency of 7 clock cycles, including 2 clock cycles for detection.

Keywords
hardware security GPRs fault recovery embedded processor
Published
2023-04-29
Appears in
SpringerLink
http://dx.doi.org/10.1007/978-3-031-31420-9_8
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