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Cognitive Computing and Cyber Physical Systems. Third EAI International Conference, IC4S 2022, Virtual Event, November 26-27, 2022, Proceedings

Research Article

Information Theoretic Heuristics to Find the Minimal SOP Expression Considering Don’t Care Using Binary Decision Diagrams

Cite
BibTeX Plain Text
  • @INPROCEEDINGS{10.1007/978-3-031-28975-0_8,
        author={N. Padmavathy and K. S. Jhansi and K. Ormila and B. Valarmathi},
        title={Information Theoretic Heuristics to Find the Minimal SOP Expression Considering Don’t Care Using Binary Decision Diagrams},
        proceedings={Cognitive Computing and Cyber Physical Systems. Third EAI International Conference, IC4S 2022, Virtual Event, November 26-27, 2022, Proceedings},
        proceedings_a={IC4S},
        year={2023},
        month={3},
        keywords={Binary decision diagrams Boolean expression Entropy Logic gates Karnaugh map Minimal SOP Quine McClusky method},
        doi={10.1007/978-3-031-28975-0_8}
    }
    
  • N. Padmavathy
    K. S. Jhansi
    K. Ormila
    B. Valarmathi
    Year: 2023
    Information Theoretic Heuristics to Find the Minimal SOP Expression Considering Don’t Care Using Binary Decision Diagrams
    IC4S
    Springer
    DOI: 10.1007/978-3-031-28975-0_8
N. Padmavathy1,*, K. S. Jhansi1, K. Ormila2, B. Valarmathi3
  • 1: Department of Electronics and Communication Engineering, Vishnu Institute of Technology
  • 2: Department of Electrical and Electronics Engineering
  • 3: Department of Software and Systems Engineering, School of Information Technology and Engineering, Vellore Institute of Technology
*Contact email: padmavathy.n@vishnu.edu.in

Abstract

Logic minimization plays a significant part in decreasing the complexity of the circuit since the number of Gates will be diminished… Till today, the conventional or traditional approaches like Boolean laws; Karnaugh map; Quine-Mccluskey are in existence for Boolean expression simplification. The above approaches have several drawbacks; to name a few – logical synthesis complexity, multiple solutions using k-maps, the number of cells increases exponentially with number of variables in a Boolean function and more computational time is needed while solving using Quine Mccluskey. Moreover, the implementation of k-map and Quine-Mccluskey method is difficult in logic synthesis of chip design. The solution to all above drawbacks is the use of Binary Decision Diagrams which is faster and its applicability to large circuits is possible. The main purpose of this work is to reduce the Boolean expressions considering DC function and also to calculate the entropy of the simplified Boolean expression using binary decision diagrams.

Keywords
Binary decision diagrams Boolean expression Entropy Logic gates Karnaugh map Minimal SOP Quine McClusky method
Published
2023-03-25
Appears in
SpringerLink
http://dx.doi.org/10.1007/978-3-031-28975-0_8
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