Efficient Architecture for a High Performance Authenticated Encryption Algorithm on Reconfigurable Computing

High performance authenticated encryption algorithms are indispensable and preferable for securing the contemporary high speed wireless networks as they can perform their tasks without affecting overall performance of the network, and can provide data confidentiality, data integrity, and authentication cryptographic services simultaneously. Most of existing FPGA based architectures that have been proposed to enhance performance of such algorithms considered generic FPGA fabrics for implementations. Implementing complex algorithms using only traditional FPGA logic requires large amount of such resources that in turn can affect performance. In this work, an efficient architecture for AEGIS-128 authenticated encryption algorithm is proposed using both FPGAs’ embedded hard-cores such as digital signal processing slices and block random access memories that have not been fully exploited for such applications with balanced amount of generic logic. The aim is to reduce performance bottlenecks and enhance performance of AEGIS-128. The implementation results show that the proposed architecture outperforms existing similar approaches found in the literature in terms of throughput, and utilization of reduced amount of resources.