Research Article
Hardware/Software Co-design for Convolutional Neural Networks Acceleration: A Survey and Open Issues
@INPROCEEDINGS{10.1007/978-3-030-93179-7_13, author={Cuong Pham-Quoc and Xuan-Quang Nguyen and Tran Ngoc Thinh}, title={Hardware/Software Co-design for Convolutional Neural Networks Acceleration: A Survey and Open Issues}, proceedings={Context-Aware Systems and Applications. 10th EAI International Conference, ICCASA 2021, Virtual Event, October 28--29, 2021, Proceedings}, proceedings_a={ICCASA}, year={2022}, month={1}, keywords={Hardware/software co-design Convolutional neural networks FPGA ASIC}, doi={10.1007/978-3-030-93179-7_13} }- Cuong Pham-Quoc
Xuan-Quang Nguyen
Tran Ngoc Thinh
Year: 2022
Hardware/Software Co-design for Convolutional Neural Networks Acceleration: A Survey and Open Issues
ICCASA
Springer
DOI: 10.1007/978-3-030-93179-7_13
Abstract
In this paper, we survey hardware/software co-design approaches in the literature to accelerate Convolutional neural networks, one of the two successful forms of Deep Neural Networks. We classify these approaches according to target platforms used to accelerate CNNs, including FPGA-based and ASIC-based. Due to the flexibility of FPGAs, we mainly focus on FPGA-based designs. These designs are categorized into sub-classes according to optimization techniques used. We then analyze in detail to compare FPGA-based hardware accelerator systems for CNNs regarding working frequency and performance efficiency. Through the survey, we also identify open issues for this research topic. These challenges can be research directions for optimizing performance, accuracy, and energy consumption of hardware accelerator systems for CNN using the hardware/software co-design approach.
