Research Article
Mitigation of Low-Frequency Oscillations by Tuning Single-Phase Phase-Locked Loop Circuits
@INPROCEEDINGS{10.1007/978-3-030-73585-2_9, author={Dayane M. Lessa and Michel P. Tcheou and Cleiton M. Freitas and Lu\^{\i}s Fernando C. Monteiro}, title={Mitigation of Low-Frequency Oscillations by Tuning Single-Phase Phase-Locked Loop Circuits}, proceedings={Sustainable Energy for Smart Cities. Second EAI International Conference, SESC 2020, Viana do Castelo, Portugal, December 4, 2020, Proceedings}, proceedings_a={SESC}, year={2021}, month={4}, keywords={Phase-Locked Loop Orthogonal signal generators Tuning methodology Low-frequency oscillations}, doi={10.1007/978-3-030-73585-2_9} }- Dayane M. Lessa
Michel P. Tcheou
Cleiton M. Freitas
Luís Fernando C. Monteiro
Year: 2021
Mitigation of Low-Frequency Oscillations by Tuning Single-Phase Phase-Locked Loop Circuits
SESC
Springer
DOI: 10.1007/978-3-030-73585-2_9
Abstract
Phase-Locked Loop (PLL) circuits have contributed to modernising electrical grids in different segments, such as distributed generation, identification and characterisation of phenomena related to power quality, localisation of faults, among others. This justifies the undergone research aiming at increasing their performance under certain conditions. Taking the example of the single-phase PLLs, researchers have worked out ways to cope with the characteristic doubly-frequency oscillation, which can undermine the performance of the frequency and phase tracking and compromise the extraction of the fundamental component from the input signal. In this sense, the present article aims at analysing a single-phase PLL circuit providing a methodology to adjust the control gains and minimise low-frequency oscillation. As for the analysed PLL, simulations in the time domain were carried out for modified versions of the well-known E-PLL, SOGI-PLL, and APF-PLL, all of them comprising notch filters and to cope with the doubly-frequency oscillation.
