Research Article
Pipelined BP Polar Decoder with a Novel Updated Scheme
@INPROCEEDINGS{10.1007/978-3-030-69072-4_47, author={Xiaojun Zhang and Na Li and Jun Li and Chengguan Chen and Hengzhong Li and Geng Chen}, title={Pipelined BP Polar Decoder with a Novel Updated Scheme}, proceedings={Wireless and Satellite Systems. 11th EAI International Conference, WiSATS 2020, Nanjing, China, September 17-18, 2020, Proceedings, Part II}, proceedings_a={WISATS PART 2}, year={2021}, month={2}, keywords={Polar code Belief propagation (BP) VLSI Pipelined architecture Hardware efficiency}, doi={10.1007/978-3-030-69072-4_47} }- Xiaojun Zhang
Na Li
Jun Li
Chengguan Chen
Hengzhong Li
Geng Chen
Year: 2021
Pipelined BP Polar Decoder with a Novel Updated Scheme
WISATS PART 2
Springer
DOI: 10.1007/978-3-030-69072-4_47
Abstract
Compared with the SC decoder, BP decoder provides a higher throughput and lower decoding latency for its inherent parallel nature. However, the functional units of existing BP decoders are not fully utilized. In this paper, we propose a new update scheduling scheme and hardware optimization design to improve the hardware efficiency of BP decoder. First, a pipelined decoder architecture is proposed to reduce the consumption of functional units. Then, a new update scheduling scheme is proposed, when updating the messages, both new-value and old-value approaches are used to improve the utilization of functional units and reduce the decoding latency. The analysis and synthesis results have shown that, compared with the existing methods, the proposed decoder suffers from a slight the decoding performance degradation, but the utilization rate of basic computational blocks (BCB) can be increased to 50.58%. The storage resource dissipation can be reduced by 20.1%–34.09%.
