Artificial Intelligence for Communications and Networks. Second EAI International Conference, AICON 2020, Virtual Event, December 19-20, 2020, Proceedings

Research Article

FTEI: A Fault Tolerance Model of FPGA with Endogenous Immunity

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  • @INPROCEEDINGS{10.1007/978-3-030-69066-3_48,
        author={Jie Wang and Shuangmin Deng and Junjie Kang and Gang Hou},
        title={FTEI: A Fault Tolerance Model of FPGA with Endogenous Immunity},
        proceedings={Artificial Intelligence for Communications and Networks. Second EAI International Conference, AICON 2020, Virtual Event, December 19-20, 2020, Proceedings},
        proceedings_a={AICON},
        year={2021},
        month={7},
        keywords={FPGA Fault tolerance Fault detection Fault recover},
        doi={10.1007/978-3-030-69066-3_48}
    }
    
  • Jie Wang
    Shuangmin Deng
    Junjie Kang
    Gang Hou
    Year: 2021
    FTEI: A Fault Tolerance Model of FPGA with Endogenous Immunity
    AICON
    Springer
    DOI: 10.1007/978-3-030-69066-3_48
Jie Wang1, Shuangmin Deng1, Junjie Kang1, Gang Hou1
  • 1: Dalian University of Technology

Abstract

FPGA emerges as a very promising AI chip and algorithm hardware accelerator. However, the FPGA is susceptible to complex and changeable environment, which leads to circuit configuration information faults. To address this issue, we propose FTEI, a fault tolerance model of FPGA with endogenous immunity. At fault detection phase, we put forward a fault detection models based on optimized logistic regression classification and use it to establish a fault model matching library. During fault recover stage, we use fault configuration library and online evolution to recover faults. In order to improve the success ratio of online evolution, we propose RLAGA, an adaptive genetic algorithm based on reinforcement learning. Experiments on typical functional circuits, 8-bit parity verifier and 2-bit multiplier, demonstrate that the fault detection accuracy rates reach 94.4% and 93.2%, and the fault recover success rates of RLAGA are 100% and 90%, which significantly improves FPGA errors detection and recover effectiveness.