Research Article
Multi-list Design and FPGA Implementation Method of OLSR protocol
@INPROCEEDINGS{10.1007/978-3-030-67514-1_38, author={Hongyu Zhang and Bo Li and Zhongjiang Yan and Mao Yang}, title={Multi-list Design and FPGA Implementation Method of OLSR protocol}, proceedings={IoT as a Service. 6th EAI International Conference, IoTaaS 2020, Xi’an, China, November 19--20, 2020, Proceedings}, proceedings_a={IOTAAS}, year={2021}, month={1}, keywords={Ad Hoc OLSR FPGA Memory management}, doi={10.1007/978-3-030-67514-1_38} }- Hongyu Zhang
Bo Li
Zhongjiang Yan
Mao Yang
Year: 2021
Multi-list Design and FPGA Implementation Method of OLSR protocol
IOTAAS
Springer
DOI: 10.1007/978-3-030-67514-1_38
Abstract
Ad Hoc network is a new networking technology that does not rely on preset communication facilities, and is one of the important components of the next generation wireless communication network system. The OLSR (Optimized Link State Routing) protocol is a classic proactive routing protocol in Ad Hoc networks. Most of the existing research is based on software, there has not been a case of using hardware to implement the OLSR protocol. The core of implementing OLSR protocol based on FPGA (Field Programmable Gate Array) is the design of memory management table. This paper proposes a multi-link list design and FPGA implementation method, which effectively avoids the conflicts that will arise when using memory management tables.
