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IoT as a Service. 6th EAI International Conference, IoTaaS 2020, Xi’an, China, November 19–20, 2020, Proceedings

Research Article

A Flowchart Based Finite State Machine Design and Implementation Method for FPGA

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  • @INPROCEEDINGS{10.1007/978-3-030-67514-1_24,
        author={Zhongjiang Yan and Hangchao Jiang and Bo Li and Mao Yang},
        title={A Flowchart Based Finite State Machine Design and Implementation Method for FPGA},
        proceedings={IoT as a Service. 6th EAI International Conference, IoTaaS 2020, Xi’an, China, November 19--20, 2020, Proceedings},
        proceedings_a={IOTAAS},
        year={2021},
        month={1},
        keywords={Flowchart Finite state machine FPGA},
        doi={10.1007/978-3-030-67514-1_24}
    }
    
  • Zhongjiang Yan
    Hangchao Jiang
    Bo Li
    Mao Yang
    Year: 2021
    A Flowchart Based Finite State Machine Design and Implementation Method for FPGA
    IOTAAS
    Springer
    DOI: 10.1007/978-3-030-67514-1_24
Zhongjiang Yan1,*, Hangchao Jiang1, Bo Li1, Mao Yang1
  • 1: School of Information and Electronics, Northwestern Polytechnical University
*Contact email: zhjyan@nwpu.edu.cn

Abstract

The design idea of control and data separation is an effective means to realize the complex communication system, and the control part can usually be designed and realized by means of finite state machine (FSM). However, there is no effective method to realize the complex communication system based on finite state machine in the existing research. Aiming at the problem of the existing FPGA design and implementation methods with complex and non-universal communication protocol and algorithm design, a Flowchart based Finite State Machine (F-FSM) design and implementation method for FPGA is proposed, which significantly improves the FPGA development efficiency. This method takes the flowchart describing the complex communication system as input, divides the communication system into modules, and outputs the finite state machine transition diagram and transition matrix of the control module. This method can effectively shorten the design time of the communication system and its control module. Finally, an IP core encapsulated in FPGA is designed. This method can effectively improve the development efficiency of control module, improve the re-usability of control module and reduce the workload of code development.

Keywords
Flowchart Finite state machine FPGA
Published
2021-01-31
Appears in
SpringerLink
http://dx.doi.org/10.1007/978-3-030-67514-1_24
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