Research Article
FPGA-Based Neural Network Acceleration for Handwritten Digit Recognition
@INPROCEEDINGS{10.1007/978-3-030-67514-1_15, author={Guobin Shen and Jindong Li and Zhi Zhou and Xiang Chen}, title={FPGA-Based Neural Network Acceleration for Handwritten Digit Recognition}, proceedings={IoT as a Service. 6th EAI International Conference, IoTaaS 2020, Xi’an, China, November 19--20, 2020, Proceedings}, proceedings_a={IOTAAS}, year={2021}, month={1}, keywords={Convolutional neural network (CNN) High-Level Synthesis (HLS) Acceleration FPGA}, doi={10.1007/978-3-030-67514-1_15} }- Guobin Shen
Jindong Li
Zhi Zhou
Xiang Chen
Year: 2021
FPGA-Based Neural Network Acceleration for Handwritten Digit Recognition
IOTAAS
Springer
DOI: 10.1007/978-3-030-67514-1_15
Abstract
Convolutional neural network (CNN) has been widely employed in different engineering fields, as it achieves high performance for enormous applications. However, neural networks are computationally expensive and require extensive memory resource. While still implementing convolutional neural network using relatively few resources but achieving high computation speed has been an active research. In this paper, we propose an FPGA-based handwritten digit recognition acceleration method, applying the Lenet-5 model to the FPGA using Vivado High-Level Synthesis. By using fixed point quantization method, removing data dependencies and applying appropriate pipelining, the accuracy rate reaches 97.6% on MNIST dataset. On Zedboard, we achieve 3.65 times faster than running only on the Processing System (PS) of the same hardware.
