Research Article
Design and Implementation of Assembler for High Performance Digital Signal Processor (DSP)
@INPROCEEDINGS{10.1007/978-3-030-41114-5_56, author={Peng Ding and Haoqi Ren and Zhifeng Zhang and Jun Wu and Fusheng Zhu and Wenru Zhang}, title={Design and Implementation of Assembler for High Performance Digital Signal Processor (DSP)}, proceedings={Communications and Networking. 14th EAI International Conference, ChinaCom 2019, Shanghai, China, November 29 -- December 1, 2019, Proceedings, Part I}, proceedings_a={CHINACOM}, year={2020}, month={2}, keywords={5G DSP GADL SA}, doi={10.1007/978-3-030-41114-5_56} }- Peng Ding
Haoqi Ren
Zhifeng Zhang
Jun Wu
Fusheng Zhu
Wenru Zhang
Year: 2020
Design and Implementation of Assembler for High Performance Digital Signal Processor (DSP)
CHINACOM
Springer
DOI: 10.1007/978-3-030-41114-5_56
Abstract
With the rapid development of the fifth-generation mobile communication technology (5G), existing digital signal processors (DSP) on the market cannot efficiently provide the performance required by some applications. In this situation, we design a new DSP with faster speed, lower latency and higher performance. In this article, based on the new DSP which can adapt to the new technology of 5G, we designed an assembler called Swift Assembler (SA). Different from the traditional assembler, SA is based on the Gnu Architecture Description Language, (GADL). We perform semantic analysis on GADL description files and then with the help of flex, bison and Binutils, the assembler is compiled and generated. With the support of GADL, SA has a clearer architecture and better scalability. At the same time, it covered the underlying implementation. Benefit from this, programmers can modify its source code with no need to understand the underlying implementation process. In this way, the design of interdependent hardware and software can be more easily.
