Research Article
System Level Performance Analysis of Designed LNA and Down Converter for IEEE 802.11ad Receiver
@INPROCEEDINGS{10.1007/978-3-030-20615-4_2, author={S. Pournamy and Navin Kumar}, title={System Level Performance Analysis of Designed LNA and Down Converter for IEEE 802.11ad Receiver}, proceedings={Ubiquitous Communications and Network Computing. Second EAI International Conference, Bangalore, India, February 8--10, 2019, Proceedings}, proceedings_a={UBICNET}, year={2019}, month={5}, keywords={Low noise amplifier Radio frequency Error vector magnitude}, doi={10.1007/978-3-030-20615-4_2} }- S. Pournamy
Navin Kumar
Year: 2019
System Level Performance Analysis of Designed LNA and Down Converter for IEEE 802.11ad Receiver
UBICNET
Springer
DOI: 10.1007/978-3-030-20615-4_2
Abstract
A low noise amplifier (LNA) operating at millimeter wave (mmWave) frequency and a down converter suitable for IEEE 802.11ad receiver is designed in a 65 nm radio frequency (RF)-CMOS low leakage (LL) process. These designed blocks are integrated in a super heterodyne receiver architecture and the overall performance of the receiver is analyzed. The designed LNA gives a performance metric of 20 dB of gain, 1.7 dB of noise figure (NF) and −7.78 dBm of IIP3. Modified Gilbert cell topology is used for down converter which gives a conversion gain of 1.5 dB from 57 GHz to 66 GHz, input P of −7.8dBm and IIP3 of 8.78 dBm with RF at 57.24 GHz from a 1.2 V supply voltage and a 1Vpp of local oscillator (LO) drive. The obtained IIP3 is 10.08 dB higher than the conventional Gilbert cell and offers an error vector magnitude (EVM) improvement of −23 dB at the receiver. This work provides RF designers a comprehensive understanding of system and circuit level on pre silicon base.
