Research Article
Design and Analysis of Low-Transition Address Generator
@INPROCEEDINGS{10.1007/978-3-030-15357-1_19, author={Sivasankaran Saravanan and Mikias Hailu and G. Gouse and Mohan Lavanya and R. Vijaysai}, title={Design and Analysis of Low-Transition Address Generator}, proceedings={Advances of Science and Technology. 6th EAI International Conference, ICAST 2018, Bahir Dar, Ethiopia, October 5-7, 2018, Proceedings}, proceedings_a={ICAST}, year={2019}, month={3}, keywords={Address generator Gray code counter Memory built in self-test (MBIST) Low power switching Linear Feedback Shift Register (LFSR)}, doi={10.1007/978-3-030-15357-1_19} }- Sivasankaran Saravanan
Mikias Hailu
G. Gouse
Mohan Lavanya
R. Vijaysai
Year: 2019
Design and Analysis of Low-Transition Address Generator
ICAST
Springer
DOI: 10.1007/978-3-030-15357-1_19
Abstract
In high-speed Nano-scale VLSI designs, memory plays a vital role of operation. Built-In Self-Test (BIST) for memory is an essential element of the system-on-chip (SoC). Investigating memory with low power techniques have been emerging in the market. Address generators to access memory cores consecutively should have low transition. This paper, attempted to put forward a proposed architecture of address generator with low-transition. In this novel technique, the address generator is constructed by a blend of modulo-counter and binary to gray code convertor with a bit-reversal block. Efficient employment of this architecture has cut-down the switching activity considerably. This proposed work compared the switching activity with conventional Linear Feedback Shift Register (LFSR), Bit-Swapping LFSR (BS-LFSR) and gray-code generator. Simulated and synthesized of the proposed architecture was done by Xilinx tool. The final result shows more than 95% reduction on dynamic power consumption related to the traditional LFSR.
