Communications and Networking. 13th EAI International Conference, ChinaCom 2018, Chengdu, China, October 23-25, 2018, Proceedings

Research Article

DSP Implementation and Optimization of Pseudo Analog Video Transmission Algorithm

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  • @INPROCEEDINGS{10.1007/978-3-030-06161-6_39,
        author={Chengcheng Wang and Pengfei Xia and Haoqi Ren and Jun Wu and Zhifeng Zhang},
        title={DSP Implementation and Optimization of Pseudo Analog Video Transmission Algorithm},
        proceedings={Communications and Networking. 13th EAI International Conference, ChinaCom 2018, Chengdu, China, October 23-25, 2018, Proceedings},
        proceedings_a={CHINACOM},
        year={2019},
        month={1},
        keywords={DSP DMA Dedicated instruction set Power allocation Turbo encoding Framing},
        doi={10.1007/978-3-030-06161-6_39}
    }
    
  • Chengcheng Wang
    Pengfei Xia
    Haoqi Ren
    Jun Wu
    Zhifeng Zhang
    Year: 2019
    DSP Implementation and Optimization of Pseudo Analog Video Transmission Algorithm
    CHINACOM
    Springer
    DOI: 10.1007/978-3-030-06161-6_39
Chengcheng Wang1,*, Pengfei Xia1,*, Haoqi Ren1, Jun Wu1, Zhifeng Zhang1
  • 1: Tongji University
*Contact email: 1631731@tongji.edu.cn, pengfei.xia@gmail.com

Abstract

With the development of wireless video technology and embedded technology, a dedicated digital signal processor (DSP) can achieve the video transmission stably and flexibly. Some existing wireless video transmission algorithms do not perform well in response to complex channel environments. A pseudo-analog video algorithm that can be run in a dedicated instruction set was proposed. At the transmitter, the image data which are removed spatially redundant are divided into L-shaped blocks for power allocation, and the digital signal are sent to CRC and Turbo coding. Finally, the modulated digital signal and the pseudo-analog data after power allocation are sent to framing. The receiver includes channel estimation and de-framing, recovers digital signal and pseudo-analog signal through error detection and decoding. We have optimized the algorithm at the assembly level, so that the entire system is more flexible. The entire transfer system will run on the FPGA and hardware DSP boards for debugging.