Research Article
A High-Speed Large-Capacity Packet Buffer Scheme for High-Bandwidth Switches and Routers
@INPROCEEDINGS{10.1007/978-3-030-06161-6_37, author={Ling Zheng and Zhiliang Qiu and Weitao Pan and Ya Gao}, title={A High-Speed Large-Capacity Packet Buffer Scheme for High-Bandwidth Switches and Routers}, proceedings={Communications and Networking. 13th EAI International Conference, ChinaCom 2018, Chengdu, China, October 23-25, 2018, Proceedings}, proceedings_a={CHINACOM}, year={2019}, month={1}, keywords={Switching system Packet buffer SRAM DRAM Queueing system}, doi={10.1007/978-3-030-06161-6_37} }- Ling Zheng
Zhiliang Qiu
Weitao Pan
Ya Gao
Year: 2019
A High-Speed Large-Capacity Packet Buffer Scheme for High-Bandwidth Switches and Routers
CHINACOM
Springer
DOI: 10.1007/978-3-030-06161-6_37
Abstract
Today’s switches and routers require high-speed and large-capacity packet buffers to guarantee a line rate up to 100 Gbps as well as more fine-grained quality of service. For this, this paper proposes an efficient parallel hybrid SRAM/DRAM architecture for high-bandwidth switches and routers. Tail SRAM and head SRAM are used for guaranteeing the middle DRAMs are accessed in a larger granularity to improve the bandwidth utilization. Then, a simple yet efficient memory management algorithm is designed. The memory space is dynamically allocated when a flow arrives, and a hard timeout is assigned for each queue. Hence, the SRAM space is utilized more efficiently. A queueing system is used to model the proposed method, and theoretical analysis is performed to optimize the timeout value. Simulation shows that the proposed architecture can reduce packet loss rate significantly compared with previous solutions with the same SRAM capacity.
