inis 18(15): e5

Research Article

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Download285 downloads
  • @ARTICLE{10.4108/eai.19-9-2018.155569,
        author={Emmannuel Ofori-Attah and Xiaohang Wang and Michael Opoku Agyeman},
        title={A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures},
        journal={EAI Endorsed Transactions on Industrial Networks and Intelligent Systems},
        volume={5},
        number={15},
        publisher={EAI},
        journal_a={INIS},
        year={2018},
        month={9},
        keywords={Dark-Silicon, Many-Core, Multi-Core, NoC, Low Power NoC Architectures, Power Budgeting},
        doi={10.4108/eai.19-9-2018.155569}
    }
    
  • Emmannuel Ofori-Attah
    Xiaohang Wang
    Michael Opoku Agyeman
    Year: 2018
    A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures
    INIS
    EAI
    DOI: 10.4108/eai.19-9-2018.155569
Emmannuel Ofori-Attah1, Xiaohang Wang2, Michael Opoku Agyeman1,*
  • 1: Department of Computing, University of Northampton, United Kingdom
  • 2: South China University of Technology, 1121 Haibin Road, Nansha, Guangzhou
*Contact email: michael.opokuagyyeman@northampton.ac.uk

Abstract

Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with many-core integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials.