On the implementation of a space time block coded transmitter in an FPGA platform

R.C.  Anguiano; G. Galaviz; A.G.   Andrade

Research Article

On the implementation of a space time block coded transmitter in an FPGA platform

Cite: BibTeX Plain Text

@INPROCEEDINGS{10.1109/WTS.2008.4547583,
    author={R.C.  Anguiano and  G. Galaviz and A.G.   Andrade},
    title={On the implementation of a space time block coded transmitter in an FPGA platform},
    proceedings={Wireless Telecommunications Symposium},
    publisher={IEEE},
    proceedings_a={WTS},
    year={2008},
    month={6},
    keywords={},
    doi={10.1109/WTS.2008.4547583}
}

R.C. Anguiano
G. Galaviz
A.G. Andrade
Year: 2008
On the implementation of a space time block coded transmitter in an FPGA platform
WTS
IEEE
DOI: 10.1109/WTS.2008.4547583

R.C. Anguiano¹, G. Galaviz¹, A.G. Andrade¹

1: Univ. Autonoma de Baja California, Mexicali

Abstract

This paper presents the implementation of a digital communications transmitter that includes a space time block encoder in an APEX20KE FPGA device from Altera. The developed transmitter includes oscillators that provide passband I-Q modulation. The complete transmitter design is appropriate for evaluation of space time block codes as well as different digital passband modulation schemes. With the reconfigurable properties of FPGA's, evaluations and new designs can be developed easily in a hardware platform. The implementation of the proposed transmitter is described, as well as the tools used in its development. The transmitter can be used as a standalone unit in a single FPGA, or as an element of a complete communication system for on-chip emulation.

Published: 2008-06-20
Publisher: IEEE

: http://dx.doi.org/10.1109/WTS.2008.4547583