Reliability Analysis for On-chip Networks under RC Interconnect Delay Variation

M.  Mondal; Xiang Wu; A. Aziz; Y.   Massoud

1st International ICST Conference on Nano-Networks

Research Article

Reliability Analysis for On-chip Networks under RC Interconnect Delay Variation

Cite: BibTeX Plain Text

@INPROCEEDINGS{10.1109/NANONET.2006.346238,
    author={M.  Mondal and Xiang Wu  and A. Aziz and Y.   Massoud},
    title={Reliability Analysis for On-chip Networks under RC Interconnect Delay Variation},
    proceedings={1st International ICST Conference on Nano-Networks},
    publisher={IEEE},
    proceedings_a={NANO-NET},
    year={2007},
    month={4},
    keywords={},
    doi={10.1109/NANONET.2006.346238}
}

M. Mondal
Xiang Wu
A. Aziz
Y. Massoud
Year: 2007
Reliability Analysis for On-chip Networks under RC Interconnect Delay Variation
NANO-NET
IEEE
DOI: 10.1109/NANONET.2006.346238

M. Mondal¹, Xiang Wu ¹, A. Aziz¹, Y. Massoud¹

1: Rice Univ., Houston, TX

Abstract

Future integrated circuits are characterized by their high defect rates thereby necessitating certain degree of redundancy. In a typical network-on-chip (NoC), multiple paths exist between a source and a sink to provide the required level of fault tolerance. Consequently, a manufacturing fault on a single interconnect does not necessarily render the resulting integrated circuit useless. In this paper we quantify the fault tolerance offered by an NoC. Specifically, we (1) provide a model for determining the probability that an NoC link fails due to manufacturing variation, and (2) measure the impact of link failure on the number of cycles taken by the NoC to implement communication

Published: 2007-04-16
Publisher: IEEE

: http://dx.doi.org/10.1109/NANONET.2006.346238