Research Article
Predictive Technology Model for Nano-CMOS Design Exploration
@INPROCEEDINGS{10.1109/NANONET.2006.346227, author={ Yu Cao and Wei Zhao }, title={Predictive Technology Model for Nano-CMOS Design Exploration}, proceedings={1st International ICST Conference on Nano-Networks}, publisher={IEEE}, proceedings_a={NANO-NET}, year={2007}, month={4}, keywords={}, doi={10.1109/NANONET.2006.346227} }- Yu Cao
Wei Zhao
Year: 2007
Predictive Technology Model for Nano-CMOS Design Exploration
NANO-NET
IEEE
DOI: 10.1109/NANONET.2006.346227
Abstract
Predictive MOSFET model is critical for early circuit design research. In this work, a new generation of predictive technology model (PTM) is developed, covering emerging physical effects and alternative structures. Based on physical models and early stage silicon data, PTM of bulk and double-gate devices are successfully generated from 130nm to 32nm technology nodes, with effective channel length down to 13nm. By tuning only ten primary parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of the current is below 10% for both NMOS and PMOS. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime