Research Article
Routing Aware Switch Hardware Customization for Networks on Chips
@INPROCEEDINGS{10.1109/NANONET.2006.346217, author={P. Meloni and S. Murali and S. Carta and M. Camplani and L. Raffo and G. De Micheli}, title={Routing Aware Switch Hardware Customization for Networks on Chips}, proceedings={1st International ICST Conference on Nano-Networks}, publisher={IEEE}, proceedings_a={NANO-NET}, year={2007}, month={4}, keywords={}, doi={10.1109/NANONET.2006.346217} }- P. Meloni
S. Murali
S. Carta
M. Camplani
L. Raffo
G. De Micheli
Year: 2007
Routing Aware Switch Hardware Customization for Networks on Chips
NANO-NET
IEEE
DOI: 10.1109/NANONET.2006.346217
Abstract
Networks on chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the evergrowing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC with low hardware overhead, matching the application requirements are essential. In this work, we present a method for reducing the hardware complexity of the NoC by automatically configuring the architecture of the NoC switches to suit the application traffic characteristics. The crossbar matrix and the arbiters of each switch in the NoC design are customized to support the traffic flows utilizing that switch. This application-specific switch customization is integrated with an existing design flow, which automates NoC topology synthesis, mapping, RTL code and physical layout generation. Several experimental studies on NoC benchmark designs are carried out, which show that the proposed switch customization technique leads to large reduction in the NoC switch area (28% on average) and power consumption (21% on average). Moreover, the critical paths of the switches reduce significantly, thereby leading to a significant speed-up of the NoC design