Research Article
A Parallelization of ECDSA Resistant to Simple Power Analysis Attacks
@INPROCEEDINGS{10.1109/COMSWA.2007.382592, author={Sarang Aravamuthan and Viswanatha Rao Thumparthy}, title={A Parallelization of ECDSA Resistant to Simple Power Analysis Attacks}, proceedings={2nd International IEEE Conference on Communication System Software and Middleware}, publisher={IEEE}, proceedings_a={COMSWARE}, year={2007}, month={7}, keywords={Algorithm design and analysis Application software Arithmetic Computer architecture Digital signatures Elliptic curves Hardware Microprocessors Parallel architectures Timing}, doi={10.1109/COMSWA.2007.382592} }- Sarang Aravamuthan
Viswanatha Rao Thumparthy
Year: 2007
A Parallelization of ECDSA Resistant to Simple Power Analysis Attacks
COMSWARE
IEEE
DOI: 10.1109/COMSWA.2007.382592
Abstract
The Elliptic Curve Digital Signature Algorithm admits a natural parallelization wherein the point multiplication step can be split in two parts and executed in parallel. Further parallelism is achieved by executing a portion of the multiprecision arithmetic operations in parallel with point multiplication. This results in a saving in timing as well as gate count when the two paths are implemented in hardware and software. This article attempts to exploit this parallelism in a typical system context in which a microprocessor is always present though a hardware accelerator is being designed for performance. We discuss some implementation aspects of this design with reference to power analysis attacks. We show how the Montgomery point multiplication and the binary extended gcd algorithms can be adapted to prevent simple power analysis attacks. We implemented our design using a hardware/software parallel architecture. We present the results when the software component is coded on an 8051 architecture and an ARM7TDMI processor. Our enhancements find applications in security environments such as servers, smart cards etc.
