Design of Low Power FSM Using Verilog in VLSI

Himani Mittal; Dinesh Chandra; Arvind Tiwari

Quality, Reliability, Security and Robustness in Heterogeneous Networks. 9th International Conference, QShine 2013, Greader Noida, India, January 11-12, 2013, Revised Selected Papers

Research Article

Design of Low Power FSM Using Verilog in VLSI

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@INPROCEEDINGS{10.1007/978-3-642-37949-9_33,
    author={Himani Mittal and Dinesh Chandra and Arvind Tiwari},
    title={Design of Low Power FSM Using Verilog in VLSI},
    proceedings={Quality, Reliability, Security and Robustness in Heterogeneous Networks. 9th International Conference, QShine 2013, Greader Noida, India, January 11-12, 2013, Revised Selected Papers},
    proceedings_a={QSHINE},
    year={2013},
    month={7},
    keywords={Heuristic Approach Mealy and Moore Machines STM (State Transition Matrix) ULP (Ultra Low Power) Power saving Entropy State Codes},
    doi={10.1007/978-3-642-37949-9_33}
}

Himani Mittal
Dinesh Chandra
Arvind Tiwari
Year: 2013
Design of Low Power FSM Using Verilog in VLSI
QSHINE
Springer
DOI: 10.1007/978-3-642-37949-9_33

Himani Mittal¹, Dinesh Chandra¹, Arvind Tiwari¹

1: J.S.S. Academy of Technical Education

Abstract

With day by day increase in integration density of CMOS technology the concern for area usage for VLSI circuits is increased,giving more importance to timing and power dissipation constraints. Controllers are running continuosly so critical for power (while parts of the data path may be shut down), and for timing because the delay through the controller may constrain the delay through the data path.

Keywords: Heuristic Approach Mealy and Moore Machines STM (State Transition Matrix) ULP (Ultra Low Power) Power saving Entropy State Codes

Published: 2013-07-09

: http://dx.doi.org/10.1007/978-3-642-37949-9_33