Research Article
Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers
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@INPROCEEDINGS{10.1007/978-3-642-32304-1_20, author={Carlos Moreno and Pilar Mart\^{\i}nez and Francisco Bellido and Javier Hormigo and Manuel Ortiz and Francisco Quiles}, title={Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers}, proceedings={IT Revolutions. Third International ICST Conference, C\^{o}rdoba, Spain, March 23-25, 2011, Revised Selected Papers}, proceedings_a={IT REVOLUTIONS}, year={2012}, month={10}, keywords={Convolution FPGA carry-save adders circular buffers}, doi={10.1007/978-3-642-32304-1_20} }- Carlos Moreno
Pilar Martínez
Francisco Bellido
Javier Hormigo
Manuel Ortiz
Francisco Quiles
Year: 2012
Convolution Computation in FPGA Based on Carry-Save Adders and Circular Buffers
IT REVOLUTIONS
Springer
DOI: 10.1007/978-3-642-32304-1_20
Abstract
In this article, we present some architectures to carry out the convolution computation based on carry–save adders and circular buffers implemented on FPGAs. Carry-save adders are not frequent in the implementation in FPGA devices, since these have a fast carry propagation path. We make use of the specific structure of the FPGA to design an optimized accumulator which is able to deal with carry–save additions as well as carry–propagate additions using the same hardware. On the other hand, this structure of circular buffers allows the convolution computation of two signals with two algorithms of calculation: the input side algorithm and the output side algorithm, in a more efficient way.
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