Scalable Information Systems. 4th International ICST Conference, INFOSCALE 2009, Hong Kong, June 10-11, 2009, Revised Selected Papers

Research Article

A Practical OpenMP Implementation of Bit-Reversal for Fast Fourier Transform

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  • @INPROCEEDINGS{10.1007/978-3-642-10485-5_15,
        author={Tien-Hsiung Weng and Sheng-Wei Huang and Ruey-Kuen Perng and Ching-Hsien Hsu and Kuan-Ching Li},
        title={A Practical OpenMP Implementation of Bit-Reversal for Fast Fourier Transform},
        proceedings={Scalable Information Systems. 4th International ICST Conference, INFOSCALE 2009, Hong Kong, June 10-11, 2009, Revised Selected Papers},
        proceedings_a={INFOSCALE},
        year={2012},
        month={5},
        keywords={Shared-memory parallel programming OpenMP Bit-reversal FFT},
        doi={10.1007/978-3-642-10485-5_15}
    }
    
  • Tien-Hsiung Weng
    Sheng-Wei Huang
    Ruey-Kuen Perng
    Ching-Hsien Hsu
    Kuan-Ching Li
    Year: 2012
    A Practical OpenMP Implementation of Bit-Reversal for Fast Fourier Transform
    INFOSCALE
    Springer
    DOI: 10.1007/978-3-642-10485-5_15
Tien-Hsiung Weng1,*, Sheng-Wei Huang1, Ruey-Kuen Perng1,*, Ching-Hsien Hsu2,*, Kuan-Ching Li1,*
  • 1: Providence University
  • 2: Chung Hua University
*Contact email: thweng@pu.edu.tw, rkperng@pu.edu.tw, robert@grid.chu.edu.tw, kuancli@pu.edu.tw

Abstract

In this paper, we describe our experience of creating an OpenMP implementation of Bit-reversal for Fast Fourier Transform programs from the existing un-parallelizable sequential algorithm. The aim of this work is to present an analysis of a case study showing the development of a shared memory parallel Bit-reversal for the FFT parallel code with practical and efficient use of multi-core machines. We present our implementation and discuss the results of the case study in terms of program improvement that may be needed to help parallel application developers with similar high performance goals. Our preliminary studies, results and experiments based on FFT code running on a four 4-cores Intel Xeon64 CPUs /Dell 6850 platform. The experimental results show that the performance of our new parallel code on 16 cores shared-memory machine are promising.