A Fully Data-Driven Reconfigurable Architecture with Very Coarse-Grained Execution Units

There is a clear turning point in the development history of reconfigurable architectures. Larger execution units (EU) used to be adopted in special domain applications to improve the cost performance of programmable architectures. However, after the granularity of EUs came up to the level of arithmetic logic unit (ALU) and multiplication accumulation unit (MAC), the trend almost stopped. At present, a great number of reconfigurable architectures make use of simple Von-Neumann-architecture processing elements (PE) with such EUs as ALU and MAC. Actually, today’s application algorithms are far different from the previous counterparts with the development over the last decades. Larger operation units can be extracted from common application algorithms. Without the coherent enhancement of EUs, it is difficult for reconfigurable architectures to replace the application specific integrated circuits (ASIC) used for most of current high-throughput applications. In order to further improve the performance/cost ratio, this paper presents a novel architecture with very-coarse-grained EUs and fully-data-driven mechanism.