Research Article
Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits
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@INPROCEEDINGS{10.1007/978-3-642-04850-0_21, author={Hu Xu and Vasilis Pavlidis and Giovanni Micheli}, title={Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits}, proceedings={Nano-Net. 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings}, proceedings_a={NANO-NET}, year={2012}, month={5}, keywords={3-D ICs repeater insertion on-chip interconnect timing optimization}, doi={10.1007/978-3-642-04850-0_21} }- Hu Xu
Vasilis Pavlidis
Giovanni Micheli
Year: 2012
Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits
NANO-NET
Springer
DOI: 10.1007/978-3-642-04850-0_21
Abstract
A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used for 2-D interconnects. Simulation results show that the proposed approach decreases the total wire delay up to 42% as compared to conventional approaches. The complexity of the proposed algorithm is linear to the number of planes that the wire spans.
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