Research Article
Efficient FPGA Implementation of an Integrated Bilateral Key Confirmation Scheme for Pair-Wise Key-Establishment and Authenticated Encryption
@INPROCEEDINGS{10.1007/978-3-030-15357-1_36, author={Abiy Tadesse Abebe and Yalemzewd Negash Shiferaw and Workineh Gebeye Abera and P. Kumar}, title={Efficient FPGA Implementation of an Integrated Bilateral Key Confirmation Scheme for Pair-Wise Key-Establishment and Authenticated Encryption}, proceedings={Advances of Science and Technology. 6th EAI International Conference, ICAST 2018, Bahir Dar, Ethiopia, October 5-7, 2018, Proceedings}, proceedings_a={ICAST}, year={2019}, month={3}, keywords={Authenticated encryption FPGA Hybrid cryptography Key agreement Key confirmation}, doi={10.1007/978-3-030-15357-1_36} }- Abiy Tadesse Abebe
Yalemzewd Negash Shiferaw
Workineh Gebeye Abera
P. Kumar
Year: 2019
Efficient FPGA Implementation of an Integrated Bilateral Key Confirmation Scheme for Pair-Wise Key-Establishment and Authenticated Encryption
ICAST
Springer
DOI: 10.1007/978-3-030-15357-1_36
Abstract
The purpose of this paper is to propose a bilateral key confirmation scheme which provides a trustworthy key establishment between two communicating parties. There are various cryptographic schemes proposed based on unilateral key confirmation. But, such schemes do not confirm the equality of the common secret information computed independently by each communicating party, and do not consider whether the other end is the intended owner of the shared secret. However, exchanging of the secret information blindly without verifying that both of the ends have computed the same common secret information and without ensuring the identity of the other end with whom they are communicating, can create security risks since attackers can impersonate acting as a claimed sender or recipient. The proposed work provides bilateral key confirmation for pair-wise key-establishment based on FPGA by integrating a key agreement protocol and an authenticated encryption scheme. The implementation outcomes show the proposed scheme’s reasonable hardware complexity and enhanced performance compared to existing similar works.