SIMUTOOLS 2009
QOSIM 2009SCENES 2009OMNET++ 2009

    SIMUTOOLS

    2nd International ICST Conference on Simulation Tools and Techniques

    SIMUTools 2009 is the Second International Conference on Simulation Tools and Techniques. This edition, which builds on the success of the first conference (168 participants from 31 countries), will focus on all aspects of simulation modeling and analysis. High quality papers are sought on simulati…

    SIMUTools 2009 is the Second International Conference on Simulation Tools and Techniques. This edition, which builds on the success of the first conference (168 participants from 31 countries), will focus on all aspects of simulation modeling and analysis. High quality papers are sought on simulation tools, methodologies, applications, and practices. The aim of the conference is to bring academic and industry researchers together with practitioners (from both the simulation community and from the numerous simulation user communities). The conference will address current and future trends in simulation techniques, models and practices, and foster interdisciplinary collaborative research in this area. While the main focus of the conference is on simulation tools, the conference also encourages the submission of broader theoretical and practical research contributions.

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    Editor(s): Olivier Dalle, Gabriel Wainer, Giovanni Stea and L. Felipe Perrone
    Publisher
    ICST
    ISBN
    978-963-9799-45-5
    Conference dates
    2nd–6th Mar 2009
    Location
    Rome, Italy
    Appeared in EUDL
    29th Nov 2011
    Appears in
    ACM Digital Library

    Copyright © 2011–2013 ICST

    • Turbo receivers with IT++

      Research Article in 2nd International ICST Conference on Simulation Tools and Techniques

      Bogdan Cristea

      Abstract
      This paper presents an extension of the IT++ library useful for the study of turbo receivers. Turbo receivers are implemented using basic Soft-Input Soft-Output (SISO) modules. From a programming poi…This paper presents an extension of the IT++ library useful for the study of turbo receivers. Turbo receivers are implemented using basic Soft-Input Soft-Output (SISO) modules. From a programming point of view, SISO modules are represented by methods of one C++ class. Each SISO module is defined by a specific instantiation of the Maximum A Posteriori (MAP) algorithm. Thus, various configurations of turbo receivers can be obtained. Several examples of turbo receivers together with simulation results are given.
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    • An agent-based simulation framework for cognitive radio studies

      Research Article in 2nd International ICST Conference on Simulation Tools and Techniques

      Jacek Dzikowski, Cynthia Hood

      Abstract
      The constantly growing number of wireless devices and applications makes efficient spectrum utilization critical. Cognitive radio technology offers a solution by employing opportunistic and adaptive …The constantly growing number of wireless devices and applications makes efficient spectrum utilization critical. Cognitive radio technology offers a solution by employing opportunistic and adaptive selection of transmission parameters and communication strategies. Due to the lack of general simulation tools available for analyzing cognitive radio networks, we propose an agent-based framework for cognitive radio studies. Unlike existing simulation tools, our design facilitates modeling of the physical environment along with the behavior of a network of cognitive radios. The inclusion of real-life spectrum occupancy data collected by the IIT Spectrum Observatory brings the modeled environment very close to reality. Additionally, because of its agent-based nature, our framework enables to study emergent and behavioral aspects of large and heterogeneous cognitive radio networks, an important factor that is being constantly neglected. Preliminary results show that presented solution is promising, but requires more development.
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    • WARPP: a toolkit for simulating high-performance parallel scientific codes

      Research Article in 2nd International ICST Conference on Simulation Tools and Techniques

      S.D. Hammond, G.R. Mudalige, J.A. Smith, S.A. Jarvis, J.A. Herdman, A. Vadgama

      Abstract
      There are a number of challenges facing the High Performance Computing (HPC) community, including increasing levels of concurrency (threads, cores, nodes), deeper and more complex memory hierarchies …There are a number of challenges facing the High Performance Computing (HPC) community, including increasing levels of concurrency (threads, cores, nodes), deeper and more complex memory hierarchies (register, cache, disk, network), mixed hardware sets (CPUs and GPUs) and increasing scale (tens or hundreds of thousands of processing elements). Assessing the performance of complex scientific applications on specialised high-performance computing architectures is difficult. In many cases, traditional computer benchmarking is insufficient as it typically requires access to physical machines of equivalent (or similar) specification and rarely relates to the potential capability of an application. A technique known as application performance modelling addresses many of these additional requirements. Modelling allows future architectures and/or applications to be explored in a mathematical or simulated setting, thus enabling hypothetical questions relating to the configuration of a potential future architecture to be assessed in terms of its impact on key scientific codes.

      This paper describes the Warwick Performance Prediction (WARPP) simulator, which is used to construct application performance models for complex industry-strength parallel scientific codes executing on thousands of processing cores. The capability and accuracy of the simulator is demonstrated through its application to a scientific benchmark developed by the United Kingdom Atomic Weapons Establishment (AWE). The results of the simulations are validated for two different HPC architectures, each case demonstrating a greater than 90% accuracy for run-time prediction. Simulation results, collected from runs on a standard PC, are provided for up to 65,000 processor cores. It is also shown how the addition of operating system jitter to the simulator can improve the quality of the application performance model results.
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    • Simulation of scale-free networks

      Research Article in 2nd International ICST Conference on Simulation Tools and Techniques

      Gabriele D’Angelo, Stefano Ferretti

      Abstract
      In this paper, we present a new simulation tool for scale-free networks composed of a high number of nodes. The tool, based on discrete-event simulation, enables the definition of scale-free networks…In this paper, we present a new simulation tool for scale-free networks composed of a high number of nodes. The tool, based on discrete-event simulation, enables the definition of scale-free networks composed of heterogeneous nodes and complex application-level protocols. To satisfy the performance and scalability requirements, the simulator supports both sequential (i.e. monolithic) and parallel/distributed (i.e. PADS) approaches. Furthermore, appropriate mechanisms for the communication overhead-reduction are implemented. To demonstrate the efficiency of the tool, we experiment with gossip protocols on top of scale-free networks generated by our simulator. Results of the simulations demonstrate the feasibility of our approach. The proposed tool is able to generate and manage large scale-free networks composed of thousands of nodes interacting following real-world dissemination protocols.
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    • Modeling networking issues of network-on-chip: a coloured petri nets approach

      Research Article in 2nd International ICST Conference on Simulation Tools and Techniques

      Hamid Hajabdolali Bazzaz, Marjan Sirjani, Ramtin Khosravi, Shamim Taheri

      Abstract
      Network-on-Chip (NoC) is proposed as a new scalable architecture to address the future design challenges of system-on-a-chip (SoC). As current verification techniques for on-chip communication algori…Network-on-Chip (NoC) is proposed as a new scalable architecture to address the future design challenges of system-on-a-chip (SoC). As current verification techniques for on-chip communication algorithms are typically complicated tasks including many hardware modules and software routines, verifying the algorithms themselves is almost impossible. Having the incentive for simplifying verification of these on-chip algorithms, in this paper, we propose a detailed NoC CPN model in which key NoC networking challenges, namely network topology, switching method, and routing algorithm are considered. By this model, any desired NoC topologies, including but not limited to, mesh and k-ary n-cube can be constructed. As for switching techniques, dominant on-chip switching methods, namely, packet switching, circuit switching, and wormhole switching, are modeled. Besides, as model of a NoC switch element is highly dependent on its switch fabric type, different sorts of switching fabrics, i.e., crossbar and shared bus, are modeled in this contribution. For routing the packets between cores, a CPN version of dimension-ordered routing, dominant routing algorithm for NoC, is implemented in the switches.
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