Design and Analysis of Energy Efficient Domino Logic Architectures with Single Electron Transistors in Pull Down Network and Keeper Topology

Nanotechnology and VLSI goes hand in hand. Modernization of electronics and communication systems has demanded for compactness of the devices with low power and high speed. Conventionally CMOS logic is preferred due to its low power and its high speed benefits. Researches demand a new logic style that can effectively replace conventional CMOS. Many styles including Domino logic are already gaining attention in this regard. The proposed work introduces Single Electron Transistors (SET) instead of NMOS in Pull Down Network and Keeper transistor of Domino Logic. As SETs are predominant in Nanotechnology, when employed in domino logic circuits as a fusion with normal MOS transistors will contribute effectively in terms of area, power and delay. The parameters are estimated with Cadence 45nm (SETSpice Model) technology. The proposed domino logic architectures come up with an average of 68% energy efficiency when compared with conventional CMOS circuit and its Domino logic predecessors.


Introduction
Emerging fields such as Artificial Intelligence, Machine Learning, Deep Learning, and Data Science requires compact devices with energy efficient characteristics at all levels. This compactness in area and energy efficiency has been explored over the years by researches throughout the world. Conventional CMOS logic devices have been used extensively in all VLSI circuits for its low power dissipation capabilities. Many logic styles such as Pseudo NMOS Logic, Pass Transistor Logic, Dynamic Logic and Domino Logic are already in the process of CMOS Logic for few circuits. In the proposed work, Domino logic is explored with various enhancements and optimizations. Initially Domino logic with normal NMOS & PMOS transistors were analysed [5]. Later the key element in most Nanotechnology applications called Single Electron Transistor (SET) are used instead of NMOS transistors as a hybrid combination [1,4] especially in the predominant parts of Domino Logic Style of design. This replacement has proved to be better in case of power, delay and area efficiency. This enhanced version of Domino logic style can be very helpful in applications which demand for compact circuits with good energy efficiency as well.
The research paper is organised as follows: Section 2 about an overview of SETs and their literature; Section 3 gives an insight on exploring Domino logic style of designing circuits; Section 4 deals with the idea behind proposed method. Section 5 deals with the advantage of using SET also in keeper transistor. Section 6 deals result and further inferences from the result. Section 7 concludes the paper and discusses about the future scope and research possibilities.
2 similar to normal MOSFETs except the channel which is replaced by a small dot like Tunnel Junction Diode. A vacuum or insulation layer is created by this Tunnel Junction Diode which gives the same gate capacitance (Cg) effect as that of normal MOSFET's. The gate voltage Vg is used to control the change on the Gate-Dot capacitance (Cg). The equivalent circuit of a SET and its symbolic representations are given in Figure 1. In Set, a very thin nearly 1nm thickness vacuum is the insulator which separates two piece of metals namely source and drain. The discrete electronic configuration of SET permits only one electron inside the tunnel with specific criteria. SET's are mainly explored for their faster performance than normal transmitters and can be widely explored in Single -electron memory and logic systems. But these sets can be implemented only for simple architectures. They suffer "offset charges" (i.e.,) the Vg (gate voltage) have to meet peak current which varies randomly from 1 device to other. This makes it highly impossible for complex circuits. Due to their unmatchable faster switching times, they can be implemented for denser & critical signal and image processing systems. SET research all started off with a hybrid SET-MOS architecture which was later converted to negative differential resistance architecture by shorting Gate and Drain terminals [1]. Another hybrid CMOS-SET circuit Monte Carlo Simulations were carried out to analyse its sustainability for CAD frameworks in designing IC's [2]. In order to minimize the power utilization for embedded system design [3] was proposed which quite succeeded in fulfilling the need. The gate input voltage had to be much more than the power supply for the SET for decent switching properties was proposed in [4] which eventually failed as it was practically unrealizable for building circuits.

Exploring Domino Logic Circuits
In order to overcome the occurrence of a hardware glitch because of dynamic logic, domino logic circuits were proposed. The general architectures of a domino logic stages is shown in Figure 2    The inverter creates an output (with reference to Figure 2) as follows: .This domino logic is basically noninverting in nature because of a inverter at the exit part of architecture. Domino logic works with clock values [12] in two phases. Phase I: When clock ɸ = 0, it initiates the pre changing phase where Cx pre changes to Vx = VDD. Phase II: When clock ɸ = 1, it initiates the evaluation phase when the logic corresponding to the bank of nFETs are performed. Domino logic is always preferred in cascades. (i.e.,) output of 1 st stage connected to input of next stage. But all stages are controlled by same clock signal ɸ.
Domino logic researches are going on from early 1990's. The various issues of domino logic circuits were discussed [5]. Later the variable threshold voltage keeper transistor was introduced to overcome the issues in noise margin [6].In this work, single electron transistors were used along with normal MOSFET's to overcome the issues associated with high power dissipation and more propagation delay of domino logic. Certain researches tried to incorporated single electron transistor with dynamic logic [7,13] where sets are used as pseudo transistors with great advantage that it is consistent in voltage levels and can be used for realizing hybrid circuits. A technique similar to our proposed work was elucidated in [9] but that used Fin FET Technology and analysed better noise performance and improve power delay product.

Proposed Domino Logic Architecture with SET in Pull-Down Network
Various CMOS logic architectures such as Inverter, NAND, NOR, OR, AND, EX-OR circuits were analysed. Their power, delay and area were found to be good enough for sustaining in the current scenario. But for future Nano-scale devices and technologies, we are in need of more precise and compact devices (deep sub-micron devices) [14,15] and therefore VLSI architectures. In this view, we have proposed using domino logic as an alternative to basic circuits as mentioned above. There is a twist to this switch over. We not only use normal MOSFET's, but also use SET's (Single Electron Transistor) in the architecture.
SET's are used only in the pull-down network of domino structures. Normal MOSFET's are used in the clock handling PMOS and NMOS part. This is because when clock is in pre-charge phase, the power dissipation will be higher than in the evaluation phase. To control power dissipation in pre-charge, MOSFET's are used. The architectures include for analysis are BUF, NAND2, NAND4, NOR2, NOR4, NOR8, and NOR16.
Even though SET's are used for bringing down the power consumption and area utilized. This proposed method also encounters the delay variation problem like normal domino logic. In order to overcome this delay variation, the loop and keeper transistors are utilized.

Analysis of Delay Variation
From [10], a small modification to our proposed method gave a good result even in the delay variations. Let us consider Figure 4 as a test circuitry for evaluation of delay variations. It is a well-known fact that there is always a trade-off between noise immunity and speed in domino logic circuit which basically rely on the keeper ratio (K) which is defined as the ration between saturation current of keeper transistor and overall pull down network. To overcome delay, K must be low than unity (preferably from 0.1 to 0.5). For this we need the PMOS of output in inverter four times wider than its NMOS.

Figure 4. Circuit for evaluation of delay variations
In order to analyse delay variations, the above mentioned test circuit is treated with 200 runs of Monte Carlo simulations in 45nm CMOS spice tool. The Mean (µ), Standard Deviation (σ), Variability (σ/µ) are all noted for the delay. This test is done with load capacitance to kept at a minimum value by fixing the aspect ratio of inverter and PDN network as (W/L) inv is twice that of (W/L) PDN. Mkp is sized to achieve keeper ratio K=0.1

Modifying Positive Feedback Loop to Reduce Delay Variations
A better architecture to split the keeper transistor and hence decrease its transconductance effect while keeping the same strength is shown in Figure 5.  To achieve this Wkp1 = Wkp2 = Wkpand Lkp1 + Lkp2 = Lkp is followed. Even though the transistors are split, the resistance value will be maintained as given below: Where RDynamic Resistance; µpmobility of PMOS; cox-oxide capacitance; VDDSupply voltage; Vtp-> threshold voltage of PMOS. In our proposed system, the two split keeper transistors are also replaced with Single Electron Transistor (SET's). This modification brings down delay variations as well as improves the overall working performance of the domino logic circuits, with almost 80% decrease in power consumption and 63% decrease in speed.

Design Consideration, Simulation Results and Inferences
In the proposed work, the simulations for all the architectures are carried with the following specifications.

Pre-charge and Evaluation MOSFET Specification
The aspect ratios of precharge and Evaluation transistors are considered with the specification (W/L) pre = 1 and (W/L) Eval = 1 This can be achieved if W pre = W Eval = 45nm and L pre = L Eval = 45nm

Pull Down Network SET Specification
The aspect ratios of Pull Down Network transistors are considered with the specification (W/L)PDN => series of (W/L)SETS Which are having same aspect ratio as that of pre-charge and evaluation transistors but the channel insulation layer is very thin approximately 5 to 10nm.

Keeper Transistor Specification
As per the approach proposed in [10], for the reduced delay in domino logic, keeper transistor is split into two with following specification, With these design consideration, the result obtained is 45nm CMOS Cadence SPICE tool with SET are discussed below. On an average of 10 buffer samples are considered for final values. In order to show the difference, CMOS logic is also included in the discussion of Table1.        From the above tables [1 to 7], it is inferred that when these structures are simulated and analysed in SPICE platforms like Cadence, the proposed system gives on an average an improvement of 80% improvement in power consumed and 63% improvement in speed. Thus 68% energy efficiency is obtained from the proposed architecture. This is achieved because of the effective usage of SETs in both PDN and Keeper transistors of Domino architectures. Also the delay variations are comparatively lesser than the conventional architectures of Domino logic. Moreover, the area utilized is also less making it prominent for Compact size applications especially Nano-electronics and other Nano applications.

Conclusion
The replacement of static CMOS logic in VLSI was never easier. Few steps have shown significant improvements in other logic styles as well but restricted to their applications. In this work also, the proposed hybrid architecture works with wonderful performance if used only for fundamental circuits. The effective replacement of MOSFET's with SET's both in pull down network and in keeper transistor have worked really well for improving power and delay variability performance in domino logic style. This will have its drawbacks for complex circuits as SET's will degrade noise immunity of domino. Hence, it is best suited for 6 simple basic gates which can find great application in Nano Technology like Nano electronics, Nano robotics. The future work of this paper will try to bring in SET's even more effectively into domino logic style. To conclude, this proposed work has brought 80% of power enhancement and 63% of delay improvement when compared with its predecessors.
Further this work can be continued by applying optimized aspect ratio values to SETs in PDN and keeper topology as a future work.