Evolutionary Multiobjective Optimization for Adaptive Dataflow-based Digital Predistortion Architectures★

In wireless communication systems, high-power transmitters suffer from nonlinearities due to power amplifier (PA) characteristics, I/Q imbalance, and local oscillator (LO) leakage. Digital Predistortion (DPD) is an effective technique to counteract these impairments. To help maximize agility in cognitive radio systems, it is important to investigate dynamically reconfigurable DPD systems that are adaptive to changes in the employed modulation schemes and operational constraints. To help maximize effectiveness, such reconfiguration should be performed based on multidimensional operational criteria. With this motivation, we develop in this paper a novel evolutionary algorithm framework for multiobjective optimization of DPD systems. We demonstrate our framework by applying it to develop an adaptive DPD architecture, called the adaptive, dataflow-based DPD architecture (ADDA), where Pareto-optimized DPD parameters are derived subject to multidimensional constraints to support efficient predistortion across timevarying operational requirements and modulation schemes. Through extensive simulation results, we demonstrate the effectiveness of our proposed multiobjective optimization framework in deriving efficient DPD configurations for runtime adaptation.


Introduction
In wireless communication systems, I/Q mismatch, power amplifier (PA) nonlinearities, and signal leakage in the local oscillator (LO) are implementation-related problems that must be addressed before the direct-conversion principal can be deployed. In the frequency domain of the transmitted signal, the effects of these impairments are translated as power leakage into adjacent channels. Digital predistortion (DPD) is a widely investigated technique (e.g., see [1][2][3][4][5]) to counteract such impairments by applying carefully-calculated distortion to the signal prior to transmission.
A major challenge in deploying DPD architectures for cognitive radio systems is the dynamic optimization of key DPD parameters subject to time-varying and multidimensional constraints on system performance. A general approach to such optimization is to perform efficient search at design time (i.e., off-line) across alternative DPD configurations, and to then select from the search results a set of configurations that are Pareto-optimal, and that effectively In this paper, we develop a novel framework for systematic derivation of Pareto-optimized DPD system configurations that can be applied to adaptive DPD implementations. Our framework builds on the methodology of multiobjective evolutionary algorithms (e.g., see [6]), and incorporates adaptations of this methodology to efficiently handle distinguishing characteristics of DPD system optimization. We refer to our framework for DPD system optimization as the framework for Evolutionary Adaptive DPD Implementation (EADI) or ("EADI Framework").
We demonstrate the EADI Framework in this paper by applying it to develop an adaptive DPD architecture, called the adaptive, dataflow-based DPD architecture (ADDA), where Pareto-optimized DPD parameters are derived subject to multidimensional constraints to support efficient predistortion across time-varying operational requirements and modulation schemes. While the ADDA architecture is used to concretely demonstrate the capabilities of the EADI Framework, the EADI Framework is not specific to any particular DPD architecture, and can readily be adapted to work across a variety of parameterized DPD architectures. Exploring such adaptations is a useful direction for future work that emerges from the developments of this paper.
The design evaluation metrics (optimization objectives) targeted in our development of the EADI Framework and ADDA architecture in this paper are system energy consumption, adjacent channel power ratio (ACPR), and system accuracy. We abbreviate this set of metrics as EAA.
The ADDA is a parameterized architecture that can be configured dynamically to achieve a range of EAA tradeoffs. The DPD design space that we consider consists of three design parameters: the polynomial order, bit-width, and filter order. This design space is modeled in the EADI Framework, and optimization results from the framework are used to extract a subset of generated Pareto-optimized configurations (settings of the DPD parameter values). This subset of configurations provides the set of DPD system modes that will be implemented in the ADDA architecture. The set of DPD modes provided in the ADDA configuration set is made available during operation such that predistortion tradeoffs can be reconfigured among the different options in the configuration set based on dynamically changing operational requirements.
To demonstrate and experiment with the ADDA, we apply the lightweight dataflow environment (LIDE), which is a design tool for dataflow-based design and implementation of signal processing systems [7]. Dataflow graphs provide a useful form of model-based design in many areas of signal processing, and wireless communications (e.g., see [8]). We map the signal flow structure of the ADDA into actors (dataflow-based signal processing components) in LIDE, and implement the internal functionality of these actors using the Verilog hardware description language (HDL).
We demonstrate the effectiveness of the EADI Framework through extensive simulations, and validate the capabilities of the ADDA through hardware synthesis.

Related Work
Unlike earlier DPD architectures (e.g., see [2,9]), the DPD algorithm proposed in [10] is one of the first DPD techniques that jointly compensates for PA nonlinearities and I/Q modulator impairments. Conventional digital predistorters are constructed using serial configurations. For example, the work in [2] is focused on modeling and compensation of frequency-dependent gain/phase imbalance and DC offset. For more details on this serial digital predistorter structure, we refer the reader to [2]. Instead of using a serial structure, the DPD architecture in [10] employs an extended parallel Hammerstein structure, which decomposes DPD operation into direct and conjugate predistortion subsystems. Such a decomposed structure provides additional degrees of freedom in system design. In this paper, we exploit the decomposed, parallel structure of the DPD method introduced in [10], and we present new methods to search the design space, and derive Pareto-optimized realizations for this form of DPD architecture.
In architectures for cognitive radios, adaptive DPD systems that operate under Pareto-optimized configurations are highly desirable due to the multidimensional space of relevant implementation metrics. However, prior work on systemlevel DPD optimization has emphasized single-objective optimization of ACPR [1,5]. These works employ a form of search technique called genetic algorithms, which are closely related to evolutionary algorithms, to optimize DPD ACPR performance. However, the resulting solutions may not be efficient in terms of energy consumption or accuracy. Furthermore, the underlying design methodology does not produce multiple alternative configurations that may be employed for dynamic reconfiguration based on time-varying changes in operational requirements. The methods that we develop in this paper address these limitations, respectively, through development of the (1) EADI Framework for multidimensional, Pareto-optimized DPD configuration, and (2) ADDA for reconfigurable DPD architecture implementation based on configurations that are derived by the EADI Framework.
The DPD design optimization problem addressed in our work can be viewed as a multiobjective optimization problem, where the multiple objectives are generally conflicting, preventing simultaneous optimization of all objectives. One approach to such a problem is to transform all of the objective functions into a single composite function -a common method for such an approach is to use a weighted sum of the objective functions. In this case, small changes to the weights may lead to large differences in the solution set, and proper selection of the weights can be a major problem. Also, the optimization method generally returns a solution set that is preferred by the applied weights, and thus has less diversity [11]. Another general approach is to attempt to compute a representative subset of the entire Pareto set of design points. The EADI framework developed in this paper adopts this second approach, and therefore, does not suffer from the aforementioned limitations of the weighted sum approach.
A preliminary version of this paper has been presented in [12]. This paper goes beyond the previous optimization framework presented in [12] by employing fidelity-based validation of our employed power estimation approach, and applying an improved system accuracy measurement for DPD design space exploration. More specifically, in Section 4, computation of estimation fidelity is integrated to verify the accuracy of the proposed power estimator, and the EVM measurement is modified to better represent the accuracy of the system. In Section 6, the simulation results are updated based on this new EVM measurement approach. Additionally, we have extended the presentation of our optimization framework with details about the DPD algorithm employed, and the multiobjective optimization model.

Adaptive Dataflow-based DPD Architecture
The ADDA architecture developed in this paper is based on the algorithm presented in [10]. This DPD algorithm operates in two stages. In the coefficient estimation stage, the DPD filtering coefficients are estimated. The estimated coefficients are then employed in the DPD filtering stage for actual predistortion of the input signal. Since the first stage is intended for off-line computation, the ADDA architecture and EADI optimization process are focused only on the second (filtering) stage.
The structure of the predistortion filtering system is shown in Fig. 1. The DPD system is split into two branches, namely direct and conjugate predistortions. The output of the predistortion filter can be expressed as where ⋆ denotes convolution; x n and x * n are the direct and conjugate input samples, respectively; I P and I Q are the employed sets of direct and conjugate term orders, respectively; ψ p and ψ q are polynomial basis functions for the direct and conjugate branches, respectively; f p,n andf q,n are the FIR filter coefficients for the direct and conjugate polynomials, respectively; and c ′ is the LO leakage compensation component. The maximum polynomial order used can be different for the direct and conjugate branches of the predistorter [10].
Given r ∈ {p, q}, the polynomial basis function ψ r can be expressed as where I R denotes the set of term orders employed in the given DPD configuration (I R = I P if r = p, and I R = I Q if r = q); I r denotes the subset of I R that contains only of term orders up to r in I R ; and {u k,r } denotes the polynomial weights. Here, given a polynomial ρ = a 0 + a 1 x + . . . + a n x n , we define each monomial a i x i to be a term of ρ, and we define i to be the associated term order. According to [10], only odd-order polynomials are used to avoid the computation of the square-root within |x n | k−1 , which is a computation-saving option that has been applied in the proposed implementation. Fig. 2 illustrates the dataflow model of the DPD filtering subsystem that is employed in the ADDA. Here, the mode selection actor dynamically selects the DPD operational mode based on the current application scenario (i.e., based on the current modulation and requirements on EAA) and finds the  corresponding parameter settings for that mode in its local memory, and distributes these DPD parameter values to the polynomial computation actor and all of the filter actors. Following [10], we decompose the signal processing for the applied DPD algorithm into separate direct and conjugate parts.
With the parameters obtained from the mode selection actor, the polynomial computation actor computes the polynomial basis function defined in Equ. 2 for both the direct and conjugate branches. The computed polynomials are then sent to their corresponding branches and filtered by the filter actors in those branches. These filter actors are implemented with integrated use of LIDE and Verilog, as described in Section 1. As shown in Fig. 2, according to Equ. 1, the filtered samples (one output sample from each filter) are summed to produce a single sample as the final predistorted output.
Based on the analysis in [3], where a similar dataflow model is constructed for the DPD algorithm in [10], most of the computation and energy consumption is concentrated in the filter actors. Thus, in this paper, we map only the filter actors to hardware, and focus our design optimization processes on the filter actors.

Optimization Metrics
In this subsection, we elaborate on the three objectives in our targeted design optimization problem. As defined in Section 1, we refer to these metrics collectively as EAA.
Energy Measurement. As explained in Section 3, we focus our energy measurement on the energy consumed by 3 EAI Endorsed Transactions on Cognitive Communications 12 2016 -02 2017 | Volume 3 | Issue 10 | e3 the filtering subsystem, and the figure of merit that we employ is the filtering energy expended to producing a single output sample, which is denoted by the energy per sample (eps). To calculate eps, we use the total power consumption of all FIR filters used in the predistortion subsystem, which we denote as P FIR . The eps metric is then defined as eps = P FIR × C/F, where C represents the average number of clock cycles required by the filter actors to process a single new input sample, and F represents the clock frequency. In our design, both F and C are fixed for each configuration. Thus, eps is proportional to P FIR , and we can therefore use P FIR as optimization objective for our evolutionary algorithm process. Also, we report results for P FIR in Section 6 (instead of eps) as our assessment of the energy efficiency of each configuration.
We implement the DPD filtering subsystem using the Altera EP2C35F672C6 FPGA from the Cyclone II family. To facilitate efficient design space exploration within the EADI optimization process, we model the power consumption as a function of the design vector [P Q BW T FO T ] T . The definitions of the quantities P, Q, BW and FO are given in Section 5. Our approach to system-level DPD power estimation starts by first measuring the total power consumption of a single branch under all valid filter order and bit-width values using Altera PowerPlay Analyzer. The power consumption for a specific DPD configuration is then estimated as where I P and I Q are the set of direct branches and conjugate branches, respectively; bw x and fo x are the bit-width and filter order for branch x, respectively, and Power x (bw x , fo x ), the power consumed by branch x with bit-width bw x and filter order fo x , is obtained from the aforementioned power measurement process.
During MOO, we are interested in the power comparison result of two configurations instead of their actual power consumption levels. This is because, as we explore different pairs of design points during the search process, we are interested in determining which configuration in any given pair is "better" than the other. Thus, we can validate the utility of the above power estimator in our estimation context using the estimation fidelity, which is defined by (e.g., see [13]): where M is the number of configurations that we generate to calculate the fidelity. Here, , and f ij = 0 otherwise. The terms S i and S j denote the simulated average power consumption levels of configurations i and j, respectively; F i and F j are the corresponding estimates from the power estimation function We generate 100 uniformly distributed system configurations to calculate the fidelity of the power estimators used in our work for three LTE modulation schemes -QPSK, 16-QAM, and 64-QAM. The respective fidelity values resulting from these experiments are 0.79, 0.78, and 0.81. The proposed power estimation method and corresponding fidelity calculation method are not restricted to FPGA implementation, and can be adapted readily to implementations on other types of platforms. ACPR Measurement. ACPR is a metric that is commonly used to assess the extent of out-of-band energy leakage [4]. ACPR is defined as the ratio of the mean power centered on the adjacent channel to the mean power centered on the desired channel, as shown in (5).
Here, S(ω) denotes the power spectral density of the postdistorter input signal s n , and ω A and ω D denote the frequency bands of the adjacent channel and desired channel, respectively.
Accuracy Measurement. We measure the accuracy of candidate DPD designs by the error vector magnitude (EVM) and symbol error rate (SER). The former is considered as an optimization objective and the latter as a constraint on the derived configurations. The EVM measures the distortion of original symbols under the influence of non-linearities introduced by the PA and DPD. This distortion is calculated as where Pf represents a certain profile (finite sequence) X 0 (1), X 0 (2), . . . , X 0 (K) of symbols to be transmitted, and X Pf (k) is the kth actual transmitted symbol under Pf. SER is measured as the average rate of erroneous symbol transmissions. This rate is determined as where I(x) (the indicator function), has value 1 if x 0 and 0 otherwise. We require that all of the configurations extracted for mapping into the ADDA must have zero SER.

Design Space
In this section, we elaborate on the selected DPD parameters that define the predistorter design space associated with the ADDA. Polynomial Orders. As mentioned in Section 3, the DPD algorithm proposed in [10] splits its signal processing into a direct part and a conjugate part, which enables use of different polynomial orders for direct and conjugate signal terms. For example, a DPD system can be realized with fifth-order for the direct signal and only third-order for the conjugate signal. We denote the polynomial order for the direct signal and conjugate signal by P and Q, respectively. Following [10], only odd values for P and Q are considered. Thus, the number of branches (or filter actors) that is employed in a specific DPD configuration is given by N branch = (P + 1)/2 + (Q + 1)/2. In our experiments, we set the domain D of valid values for both P and Q as D = {1, 3, 5, 7, 9}. Thus, there are in total 25 P − Q combinations in our targeted design space.
Bit-widths. Intuitively, smaller bit-widths for data storage and computation lead to less energy consumption. However, signal processing accuracy may be traded off as a consequence. To incorporate this trade-off between energy efficiency and accuracy, we incorporate bit-width as a parameter of ADDA, and as a design space component of EADI. Considering requirements on system accuracy and constraints on hardware resources, we set the range of allowable bit-widths in our experiments as {5, 6, . . . , 15}. Additionally, we allow different branches to be configured with different bit-widths in the same design. This leads to great flexibility in design optimization, and a correspondingly large design space -if there are m branches used in a specific design, then the total number of valid bit-width combinations is 11 m .
Filter Orders. Similar to the bit-width design, the filter used in each branch may also have different number of coefficients. We denote this parameter as f ilter order. The filter order parameters would also significantly affect the trade-offs among EAA. The range of filter order in this work is set to be {1, 2, 3, 4, 5}.
According to the above description, our design space is too huge for exhaustive search. As a numerical example, given the aforementioned ranges for the system parameters, the design space would contain more than 55 10 configurations.

Multiobjective Optimization Using Evolutionary Algorithm
As motivated in Section 4, the DPD design space addressed in this work is a complex multidimensional space that is too large to be evaluated using exhaustive search techniques. Therefore, we apply a heuristic search strategy called evolutionary algorithms (EAs), including a particular form of EA, called strength Pareto EA (SPEA), that is suited for multiobjective optimization [6]. We select the SPEA approach due to its efficiency and scalability in addressing complex optimization problems, and its customizability to different kinds of design spaces and optimization criteria. This latter feature makes the EADI Framework readily adaptable across different kinds of DPD architectures and communication system constraints.

Problem Encoding
The parameters involved in the DPD design optimization problem are polynomial orders, bit-widths, and filter orders. Each configuration can be represented throughout the EA process by a vector, specified as [P Q BW T FO T ] T . Here, P and Q are the direct and conjugate polynomial order, respectively. As described in Section 4, the maximum number of branches considered in the design space is 10 (at most 5 branches for both the direct signals and the conjugate signals). Thus, BW is a vector with 10 dimensions representing bitwidth settings for up to 10 branches, where each dimension represents the bit-width associated with the corresponding branch. For the branches that are not used, the corresponding vector elements are set to zero. Similar conventions are applied to generate the 10-dimensional vector FO of filter order settings.
As discussed in Section 1, the objective space of the EADI Framework encompasses average power consumption, ACPR and EVM. Thus, the objective vector can be formulated as [P FIR ACPR EVM] with units (mW, dBc, %). Here, P FIR is the power consumption, as estimated by the method discussed in in Section 4, and ACPR and EVM are calculated according to (5) and (6), respectively.

Optimization Process
The EADI optimization process is executed separately for each modulation type that is to be supported in the targeted ADDA platform. The resulting Pareto-optimized configurations for the different modulation types are then collected and stored in the ADDA memory. This enables the ADDA to dynamically to select among different modulation types, and among different operational trade-offs for each modulation type.
As mentioned previously, the work flow of the EADI optimization process is based on the SPEA methodology for multidimensional search. For details on SPEA, we refer the reader to [6].
The SPEA-based optimization workflow used in our work is illustrated in Fig. 3.
According to SPEA, the population set (set of candidate solutions or individuals) ρ contains the individuals generated during each SPEA iteration, and the external setρ maintains selected non-dominated individuals among all individuals generated so far up through the current iteration. Here, we say that an individual x dominates another individual y if x is superior to y in terms of at least one design evaluation metric, and x is not inferior to y in terms of any metric. A non-dominated individual is one that is not dominated by any individual.
We initialize ρ with a well-distributed population across the design space. For each possible P − Q combination, we generate two design vectors by selecting the corresponding  bit-width and filter order values randomly from their valid ranges. Thus, the size of ρ, denoted by N, is 50 individuals.
During each iteration, each individual in ρ is evaluated to generate the objective vector [P FIR ACPR EVM]. The individuals that do not satisfy certain modulation-specific constraints (defined in Section 6) are ignored. Only the remaining non-dominated individuals are copied toρ. If the size ofρ exceeds a predefined maximum population sizē N max , a k-means clustering algorithm is used to classify the members inρ intoN max groups. This allows us to limit the size ofρ while maintaining a diverse population inρ by retaining a "representative" individual of each group inρ [6].
After updating ofρ during an optimization iteration (generation), individuals from both ρ andρ are selected to generate a "mating pool" ρ ′ . This selection process is performed randomly in a manner such that the probability of an individual's selection for the mating pool is larger for individuals with smaller fitness values. Here, "fitness" is a measure of the quality of an individual; smaller fitness values imply higher quality solutions. The recombination operator selects pairs of individuals ("parents") in ρ ′ , and for each selected pair, two new individuals ("children") are generated with probability p r .
Each generated child (from recombination) undergoes a process of random modification by a mutation operator with probability p m . After all recombination and mutation operations are completed on the mating pool ρ ′ , the resulting new population is assigned as the current population ρ for the next generation. The individuals that comprise the setρ after T generations are the Pareto-Optimized solutions obtained by the EADI Framework. Here, T is a pre-defined number of optimization iterations that is to be executed by the SPEA.
The values p r , p m , and T are design parameters of the optimization process that can be set through experimentation or by selecting commonly-used values from the literature.
These general concepts of fitness measures, recombination operators, and mutation operators are standard components of EAs. They are applied to form an optimization process that has analogies to processes by which living species evolve. However, these three operators need to be designed specifically for each optimization context. In the remainder of this section, we discuss how these operators have been designed in the EADI Framework.

Fitness Measure
Based on the SPEA approach, each individual i ∈ρ is assigned a real value S(i) ∈ [0, 1), which is referred to as the strength of i. If N represents the number of individuals in the set ρ, then S(i) is calculated as the ratio of (a) the number of individuals in ρ that are dominated by i to (b) (N + 1). The fitness of i is equal to S(i). The fitness of an individual i ∈ ρ is calculated by summing the strengths of all individuals j ∈ρ that dominate i, and then adding one to this sum. We add one to the sum here in order to guarantee that members inρ have better fitness than members in ρ (since fitness is to be minimized).

Recombination Operator
Recombination is a process of selecting parent solutions and producing child solutions from them that integrate properties of the corresponding parent solutions. The inputs of the recombination operation are the configuration vectors of the two selected parents Y 1 and Y 2 , and the outputs are either (a) the same two parents Y 1 and Y 2 (with probability (1 − p r )) or (b) the configuration vectors of two generated children (with probability p r ), denoted by C 1 and C 2 .
In the latter case (when children are generated), the process of generating each child individual C k , k = 1, 2 from the two parents is summarized as follows: (i) assign P, Q values (polynomial orders) from Y 1 or Y 2 to C k with equal probability subject to the requirement that the generated pair of P and Q values for C 1 and C 2 cannot be identical to each other; (ii) set the bit-width and filter order values of each child C k to the corresponding values of an average vector Y avg : first computes the average (Y 1 + Y 2 )/2, and for each component in this average vector that is not integer-valued, the operator replaces the component by its floor or ceiling with equal probability; and (iii) set the bit-widths and filter orders of the unused branches in the children to be zero.

Mutation Operator
In EAs, mutation operators are employed to help promote diversity from one generation of a population to the next by randomly modifying selected solution components ("genes") within individuals. In the EADI Framework for ADDA implementation, the genes for potential mutation are taken to be the vector-valued settings of BW and FO. The specific gene (BW or FO) to which modification is to be applied is selected randomly with equal probability, and then a single component of the selected vector that is to be modified is 6 EAI Endorsed Transactions on Cognitive Communications 12 2016 -02 2017 | Volume 3 | Issue 10 | e3 selected randomly (with equal probability among all vector components). The mutation operator replaces the value of the selected vector component with a uniform random value drawn between the given upper and lower bounds for that component.

Experimental Setup and Simulation Results
To validate the EADI Framework and ADDA platform, and to demonstrate their capabilities, we experiment with three LTE modulation schemes -QPSK, 16-QAM, and 64-QAM. The multiobjective optimization process is performed separately for each of the three modulation schemes, and then the resulting Pareto-optimized solution sets are integrated into the ADDA as discussed in Section 5. For all three modulation schemes, we employ the following SPEA parameter settings: (i) T = 100 (number of generations); (ii) N = 50 (population size); (iii)N max = 20 (maximum size of external set); (iv) p r = 0.8 (recombination rate); (v) p m = 0.2 (mutation rate). These values for generic SPEA settings are values that are commonly used in the literature (e.g., see [6,14]).
The constraint on ACPR used in the EADI Framework for all three modulations is −45.0 dBc. The constraints on EVM are 17.5% , 12.5%, and 8% for QPSK, 16-QAM, and 64-QAM, respectively. The constraint on SER is that it should be zero.
To help validate the effectiveness of the EADI Framework in deriving high quality DPD configurations, we apply a partial search (PS) method to solve the same multiobjective optimization problem. PS involves performing a complete search on a reduced design space. PS is also a widelyapplied method for obtaining Pareto fronts in multiobjective optimization problems (e.g., see [15]).
In our PS approach, we reduce the search space by equalizing the bit-widths and filter orders of all the filters used in all branches and apply the same valid parameter value ranges as used in the SPEA process. Thus, the reduced design space contains 5 × 5 × 11 × 5 = 1375 configurations. We evaluate these 1375 configurations exhaustively with the P FIR , ACPR, SER and EVM computations, as described in Section 4. We then remove the undesirable solutions based on the same SER, ACPR and EVM constraints as applied in the SPEA. Finally, we collect all of the non-dominated configurations from the resulting design space as the Pareto front obtained by the PS.
In the PS process, we estimate P FIR using relevant FPGA design tools (Altera PowerPlay Analyzer), while in the EADI process, we estimate P FIR using the power estimator introduced in Section 4. The estimator of Section 4 enables faster power estimation (at some expense in accuracy), which is important because very large numbers of candidate solutions are evaluated during the EADI process. For the Pareto-optimized configurations achieved by EADI, we also estimate P FIR using FPGA tools to obtain more accurate power estimation results for the derived Pareto front. In the results that we report in the remainder of this section, the comparison between the quality of the two solution sets (PS and EADI) is based on the same (more accurate) power estimation method -i.e., using FPGA tools.  The Pareto fronts derived by the EADI Framework and PS for the three selected modulations are shown in Fig. 4(a) to 4(c). We use coverage of two sets (Cov) measurements [6] to evaluate the quality of the solution sets produced by the EADI Framework and PS, which we denote by S EF and S PS , respectively. Given a multiobjective design space, and two sets α and β of candidate solutions in this space, Cov(α, β) = dom(α, β)/size(β), where dom(α, β) is the number of solutions in β that are dominated by at least one solution in α. Coverage results for each of the three modulation schemes are given in Fig. 4(a)  We also measured that the PS method requires approximately 91 hours to evaluate the three optimization metrics for the 1375 given configurations, and extract the Pareto front, while the evaluation and Pareto front extraction by the EADI Framework takes only about 1 hour. We conclude from these results involving Cov and optimization time that the EADI Framework significantly outperforms the PS method in terms of both the quality of the obtained Pareto fronts and run-time efficiency.
To concretely demonstrate DPD performance trade-offs realized in the proposed ADDA architecture, we first classify the individuals in the Pareto front obtained by EADI into three groups according to their power consumption levels. Then we select one representative individual in each group and store it in ADDA as a DPD working mode. The selected design vectors and their corresponding P FIR -ACPR-EVM measurements under three modulations in LTE are listed in Table 1. From this table, we see that for the Paretooptimized parameter settings obtained by EADI, P is always greater than or equal to Q, which validates the argument in [10] that the higher orders of the conjugate predistorters are weak, and a smaller Q value is therefore preferred. Also, in general, the branches corresponding to the lower polynomial orders are configured with higher bit-widths and filter orders compared to the branches corresponding to higher polynomial orders. This results from the the higher order signals being relatively weak for both direct and conjugate parts. Fig. 5 and Fig. 6 show the power spectral density (PSD) and constellation of the PA output without DPD, with DPD under one configuration obtained by SPEA, and with DPD under one configuration obtained by PS with a similar power level for LTE QPSK modulation as an example. PSD and constellation of the output with an ideal linear PA is also presented as a reference. It can be seen from Fig. 5 and Fig. 6 that working under the same power level, the DPD system with the configuration selected from SPEA results outperforms that with the configuration selected from PS results in terms of both ACPR and system accuracy.

Conclusions
In this paper, we have presented a novel framework, called the Evolutionary Adaptive DPD Implementation (EADI) Framework, for multiobjective optimization of digital predistortion (DPD) systems. The targeted optimization objectives include system energy consumption, adjacent channel power ratio (ACPR), and system accuracy. We apply the EADI Framework to develop an architecture, called the adaptive, dataflow-based DPD architecture (ADDA), where Pareto-optimized DPD parameter settings are derived to support efficient, adaptive predistorter operation. Simulation results demonstrate the effectiveness of the EADI Framework  in deriving efficient DPD configurations across time-varying modulation schemes subject to multidimensional constraints. The extracted Pareto-optimized configurations also help to validate assumptions in the DPD literature about preferred DPD parameter settings. Finally, the EADI Framework is shown to significantly outperform a partial search method in terms of both optimization time efficiency and the quality of the derived Pareto fronts.

Acknowledgements
This research was supported in part by Tekes, the Finnish Funding Agency for Innovation; and the U.S. National Science Foundation.