Pulse Width Insensitive Design and Verification Methods

Many embedded controllers have some critical system states that depend on an asynchronous event. Currently handling them in design depends on the availability of always-on slow clocks. In this paper we present a generic asynchronous design scheme that doesn't require a clock and ensure a reliable functionality without associated deadlock scenarios sensitive to exact arrival times of asynchronous events. This is enabled by a novel pulse width insensitive design method, which also requires unconventional verification methodology that ensures thorough and comprehensive pre-silicon design quality. These have been applied on the latest, ultra-low cost embedded micro-controller design targeted for cost sensitive applications.


Introduction
Explosion of portable, battery operated, autonomous embedded internet-of-things (IOT) market and related application require low power and low cost as the DNA for all underlying building blocks. This mandates convergence and integration of analog mixed-signal (AMS) contents, power management [1] [2][3] [4]. This situation demands smart design and verification [5] [6] approaches to address the challenges associated with low power system design and AMS integration.
Operations of electrical circuits are sensitive to input glitches i.e. pulse widths of input signals. There are issues with system level function when built with such circuit elements. For sequencing operations, delay chains are used which are critical for asynchronous data or control paths. An example system hazard is illustrated in Figure 1 wherein it is critical to reach the eventual state S-2 if it ever reached state S-1. Though in an ideal system the transition between S-1 and S-2 is considered seamless, in an actual clock-less implementation with delay elements, there is a finite time window during the state transition that is in a pseudo-state. The arrival of asynchronous event during this transition window or pseudo-state can result in the system getting stuck in an irrecoverable forbidden state. This condition will result in a system deadlock, the recovery from which requires reboot or application hard reset.
Earlier solutions implement pulse width filtering using standard glitch gobbler that may include sequential elements, delay and other combinatorial elements. The cells used in the delay elements or glitch gobbler circuits are not characterised for pulse width filtering characteristic. This mandates a 2 costlier SPICE based simulation at system level to verify the robustness of the design. Full handshake based asynchronous design methods may overcome such issues. However, systems or portions of the systems dealing with external asynchronous events that affect the system state are not amenable to such design methods.
Identified existing implementations of such systems are sensitive to pulse width of asynchronous input events. In this paper we propose a novel pulse width insensitive asynchronous design method that doesn't use any flip-flop or edge sensitive circuit elements. This scheme utilizes inherent glitch filtering behaviour of combinatorial gates. However there is no automated gate-level tools/methodology available to design, synthesize or verify such designs. To overcome this challenge we also propose a pulse width sensitive analysis capability for gate level simulation to avoid SPICE based simulations at system level.
The rest of the paper is organized into ten sections. Section 2 describes the proposed design and verification solution. Section 3 details system design aspects. Section 4 details circuit design technique. Section 5 describes the proposed design automation methodology. Section 6 describes the static timing analysis methodology. Section 7 describes the dynamic simulation based verification methodology.
An application of the proposed methodology on an example design is illustrated in section 8, while further discussion on wider application and future scope is dealt with in section 9. Section 10 concludes the paper.

Proposed design and verification solution
Standard active element based delay elements exhibit glitch filtering behaviour. This fact is not utilised in existing design practices. Such behaviour of any existing circuits cannot be analysed easily with existing standard verification techniques. This requires costly transistor level (SPICE) simulations. Pulse width insensitive design is about ordering of delay elements appropriately to achieve the required glitch filtering behaviour. Simulation based analysis methods exist for similar behaviours in sequential circuits. Combination of such verification components is extended for combinatorial elements in the proposed method.
In this paper, a novel alternate system level design technique is proposed. This is an area and power efficient circuit design technique for pulse width insensitive design which uses delay elements only. Constraints driven design automation methodology is also proposed automate the design process. This involves pulse width sensitivity characterisation of combinatorial elements, including the timing library with this additional information, and use of existing logic and physical design tools for a constraint driven automated design synthesis. A simulation based verification method that can comprehend glitch sensitivity with an extension of functional model for glitch filtering behaviour is proposed for gate level design abstraction. Delay buffers and all combinatorial logic cells exhibit inherent characteristics of pulse width filtering, pulse width modification and propagation delay.
Pulse width filtering is the minimum input pulse width that will pass through (t mpw ) a delay cell or result in a valid change in output. Pulse width modification can be elongation or compression of the pulse as illustrated in Figure 2, with compression being a predominant behaviour. Delay models exhibit two types of delay namely transport and inertial delay. Transport delay models the propagation delay of circuit. Inertial delay is a measure of the elapsed time during which a signal must persist at an input of a device in order for a change to appear at an output. It is usually modelled for clock, reset and preset controls of flip flops.
Transport delay  t mpw = t D Inertial delay  t mpw ≠ t D

Figure 2. Pulse width filtering characteristic
There are key design concerns in building delay chains. Delay chains cannot be built with any random combination of individual delay cells. For example a delay chain built with multiple instances of the same delay cell is illustrated in Figure 3. As is highlighted, when the delay cell is characterised by pulse width compression behaviour, then for all conditions when the output pulse width of any delay cell is less than the minimum pulse width allowed for a subsequent delay cell, the propagation of the input pulse through the delay chain fails. Implementations involving delay chain as part of the analog modules are easy to analyse in SPICE / transistor level (TL) simulations.
But delay chain implementation in semi-custom digital partition is difficult to analyse and verify in robust manner. 3 This paper proposes asynchronous event look-ahead as shown in Figure 4 for constraint driven design without architectural design cost. Look-ahead information is used to gate the asynchronous event for a short period during state transition window. System robustness is achieved at the cost of probabilistic loss of event in a small time window during state transition.

Circuit design technique
To arrive at a circuit design method we first analysed a delay buffer using transistor level (TL) simulations. The pulse width filtering behaviour of delay buffers are constrained by relations t mpw < t D and t mpw α t D . Hence we propose to synthesize the delay chains such that the first delay element provides the safest pulse width filtering (t D,max =t n )>t n-1 as illustrated in Fig. 5. Conventional glitch gobbling function is implemented herein but through natural property of the delay cell. First cell uses a delay cell with the largest delay (t n =t D,max ) and largest pulse width propagation (t mpw,max ).
Composition of the subsequent portion of chain is immaterial as long as all the cells obey the conditions t D < t D,max and t mpw < t mpw,max . They will not encounter any input with min. pulse width (t mpw,i > t opw,max ). It should only use cells with delay less than t D,max & t mpw <t mpw,max . This scheme is area and power efficient as it does not involve a flip-flop or latch element. Fig. 5 shows an implementation for which any input event that reaches the output of the first delay cell output (Output) will eventually result in corresponding event at the end of the delay cell (Output_eventual) without fail under any condition.

Pulse width insensitive design automation methodology
Minimum pulse width (min_pulse_width) characterization involves a custom automation along with a test bench. A test bench with two instances of the delay cells is used for simulation. One is fed with a high going pulse and other is fed with a low going pulse. The algorithm for evaluating the min_pulse_width is illustrated in Figure 6. An alternative method of characterization is as follows: 1. Infinite rise and fall delay is calculated using an input with huge pulse width.

2.
A binary search with varied pulse (say, a range of 1:25ns) input is given to cell.
3. The fail criteria is a predefined amount of (say 10%) degraded delay with respect to infinite delay.
The characterized pulse width is given as a function of input slew in Liberty format timing library file as shown in Figure 7. The Verilog model is updated to have $width constraint as shown in Figure 8.  Using the design constraints mentioned in section 4, design process can be automated as shown in Figure 9.   Commercially available vendor design synthesis tools don't support such a design process. However, based on design queries and custom automation within the vendor design tool (Ex. Cadence Genus®) framework, the pseudocode illustrated in Figure 10 can be implemented using TCL interface.

STA for pulse width sensitive timing paths
Static timing analysis (STA) for the pulse width sensitive timing paths in design can be performed using commercially available vendor design analysis tools including the synthesis (Ex. Cadence Genus®) and STA tools may be performed using the pseudocode illustrated in Figure 11.

Pulse width sensitive verification methodology
Though STA based design closure can be used to ensure all the timing requirements on the pulse width sensitive paths or arcs are met without simulation compute complexity and subjective coverage issues associated with dynamic simulations, it may not ensure the complete functional intent correctness. Hence simulation of gate level (GL) implementation is mandatory to verify complete design intent. This is primarily needed to ensure verification closure when such paths and their impact span beyond digital design partition and into mixed-signal design content.
Once the minimum pulse width characterization is done as described in previous section 5, UDP models are required to be updated to support glitch filtering as showed in Figure 12. Conventionally as described in Figure 13(a), if there is a minimum pulse width violation, UDP table drives an unknown ("X") at the output. Figure 14 Figure  13(b) that enables pulse width filtering behaviour. Figure  14 Commercially available EDA vendor tools only support SDF generation as mentioned in Figure 15.  The output pulse width is calculated based on propagation delays and input pulse widths as in the equation shown in Figure 16. An output SDF as described in Figure 17 is generated using custom automation to incorporate the minimum output pulse width IOPATH triplet.  Figure 18 shows a GLS illustration of a single delay buffer, where the proposed simulation method with appropriate SDF timing annotation is applied to enable the pulse width filtering characteristic accurately. Further the proposed design and verification methods were applied on an ultra-low power & low cost mixed-signal SoC design. Earlier identified system deadlock scenarios with conventional design method were verified to indeed cause irrecoverable state using proposed verification method. Redesign for delay chain was implemented using proposed design method. The scenarios that were earlier failing were verified to be behaving robustly in the newer design.

Discussions and future directions
Fully automated back-end flow that comprehends pulse width sensitivity for design & SDF generation can be enabled with EDA vendor engagement. Additionally formal design and verification [7][8] methods can be enabled for robustness.

Conclusions
Pulse width insensitive design and verification method is conceptualised & applied on the design. It involves a novel area and power efficient design method for pulse width insensitive design. It also introduces an automated constraints driven design synthesis methodology that can comprehend the pulse width sensitivity of the design components. Further it involves a simulation based verification method to analyse such behaviours and designs at GL abstraction. It improves the overall verification efficiency by avoiding costly SPICE based simulations to comprehend such scenarios. It allows handling reliable design of asynchronous sections in an otherwise synchronous design. Other known asynchronous design methods are difficult or costlier to apply unconditionally. Thus we enabled cost and power competitive low power design implementation for mixedsignal SoC.