Research Article
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
@INPROCEEDINGS{10.4108/ICST.NANONET2007.2033, author={Igor Loi and Federico Angiolini and Luca Benini}, title={Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow}, proceedings={2nd Internationa ICST Conference on Nano-Networks}, proceedings_a={NANO-NET}, year={2010}, month={5}, keywords={Integrated Circuits NoCs Wafer Bonding Vertical Integration.}, doi={10.4108/ICST.NANONET2007.2033} }- Igor Loi
Federico Angiolini
Luca Benini
Year: 2010
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
NANO-NET
ICST
DOI: 10.4108/ICST.NANONET2007.2033
Abstract
Three-dimensional (3D) manufacturing technologies are viewed as promising solutions to the bandwidth bottlenecks in VLSI communication. At the architectural level, Networks-on-chip (NoCs) have been proposed to address the complexity of interconnecting an ever-growing number of cores, memories and peripherals. NoCs are a promising choice for implementing scalable 3D interconnect architectures. However, the development of 3D NoCs is still at an early development stage. In this paper, we present a semi-automated design flow for 3D NoCs. Starting from an accurate physical and geometric model of Through-Silicon Vias (TSVs), we extract a circuit-level model for vertical interconnections, and we use it to evaluate the design implications of extending switch architectures with ports in the vertical direction. In addition, we present a design flow allowing for post-layout simulation of NoCs with links in all three physical dimensions.