1st International ICST Workshop on Future Network Architectures and Development Strategies

Research Article

VISTA: A New Fair Queuing Algorithm for Packet Switches

Download
  • @INPROCEEDINGS{10.4108/ICST.BROADNETS2009.7659,
        author={Xia Yu and Guo Zirong and Gao Zhijiang},
        title={VISTA: A New Fair Queuing Algorithm for Packet Switches},
        proceedings={1st International ICST Workshop on Future Network Architectures and Development Strategies},
        publisher={IEEE},
        proceedings_a={FADS},
        year={2009},
        month={11},
        keywords={Packet-based Fair Queuing, QoS guarantee, VISTA algorithm, Virtual Clock, WF2Q+},
        doi={10.4108/ICST.BROADNETS2009.7659}
    }
    
  • Xia Yu
    Guo Zirong
    Gao Zhijiang
    Year: 2009
    VISTA: A New Fair Queuing Algorithm for Packet Switches
    FADS
    IEEE
    DOI: 10.4108/ICST.BROADNETS2009.7659
Xia Yu1,*, Guo Zirong1,*, Gao Zhijiang1,*
  • 1: School of Info. Science & Tech., Southwest Jiaotong University, Chengdu 610031, China
*Contact email: rainsia@gmail.com, zirongguo@163.com, Santi1009@gmail.com

Abstract

Fairness and QoS have been main concerns in designing modern routers or switches in multimedia environment. This paper proposes a new packet-based fair queuing algorithm for packet switches called VISTA (Virtual Clock with Virtual Start Time Alignment) to improve fairness in existing VC (Virtual Clock) algorithm. A novel concept of virtual start time alignment is introduced to improve fairness of VC algorithm and to reduce the computing complexity to constant time with a hardware-based Earliest Packet Selector (EPS).