Improving per processor memory use of ns-3 to enable large scale simulations

Steven  Smith; David R.  Jefferson; Peter D.  Barnes, Jr.; Sergei  Nikolaev

Proceedings of the 2015 Workshop on ns-3

Research Article

Improving per processor memory use of ns-3 to enable large scale simulations

Cite: BibTeX Plain Text

@INPROCEEDINGS{10.1145/2756509.2756526,
    author={Steven  Smith and David R.  Jefferson and Peter D.  Barnes, Jr. and Sergei  Nikolaev},
    title={Improving per processor memory use of ns-3 to enable large scale simulations},
    proceedings={Proceedings of the 2015 Workshop on ns-3},
    publisher={ACM},
    proceedings_a={WNS3},
    year={2016},
    month={2},
    keywords={High performance computing MPI Network simulation ns-3 Parallel architecture Performance},
    doi={10.1145/2756509.2756526}
}

Steven Smith
David R. Jefferson
Peter D. Barnes, Jr.
Sergei Nikolaev
Year: 2016
Improving per processor memory use of ns-3 to enable large scale simulations
WNS3
ACM
DOI: 10.1145/2756509.2756526

Steven Smith¹, David R. Jefferson¹, Peter D. Barnes, Jr.¹, Sergei Nikolaev¹

1: Lawrence Livermore National Laboratory, Livermore, CA

Abstract

In this paper we describe enhancements to improve the scaling of the ns-3 simulator for large problem sizes. The ns-3 simulator has a parallel capability however the current implementation instantiates the entire network topology on all ranks (processors). This restricts the problem sizes that could be run. We describe an approach to removing this limitation by distributing the network topology across ranks such that each rank only holds a part of the network topology. Performance studies were conducted to investigate the scaling performance of the modified ns-3 simulator.

Keywords: High performance computing MPI Network simulation ns-3 Parallel architecture Performance

Published: 2016-02-04
Publisher: ACM

: http://dx.doi.org/10.1145/2756509.2756526