3D on-chip networking technology based on post-silicon devices for future networks-on-chip

S.  Fujita; K. Nomura; K. Abe; T.H.  Lee

1st International ICST Conference on Nano-Networks

Research Article

3D on-chip networking technology based on post-silicon devices for future networks-on-chip

Cite: BibTeX Plain Text

@INPROCEEDINGS{10.1109/NANONET.2006.346233,
    author={ S.  Fujita and K. Nomura and K. Abe and T.H.  Lee},
    title={3D on-chip networking technology based on post-silicon devices for future networks-on-chip},
    proceedings={1st International ICST Conference on Nano-Networks},
    publisher={IEEE},
    proceedings_a={NANO-NET},
    year={2007},
    month={4},
    keywords={},
    doi={10.1109/NANONET.2006.346233}
}

S. Fujita
K. Nomura
K. Abe
T.H. Lee
Year: 2007
3D on-chip networking technology based on post-silicon devices for future networks-on-chip
NANO-NET
IEEE
DOI: 10.1109/NANONET.2006.346233

S. Fujita¹, K. Nomura¹, K. Abe¹, T.H. Lee¹

1: Frontier Res. Lab., Toshiba Corp., Kawasaki

Abstract

We propose a 3D architecture using post-silicon devices, such as nano-mechanical electrical switches, carbon nanotube FETs, and nanowire FETs, for future networks-on-chip (NoC). Based on such a new 3D architecture, extremely high bandwidth with very low latency can be realized. These promising features are very useful for future NoCs

Published: 2007-04-16
Publisher: IEEE

: http://dx.doi.org/10.1109/NANONET.2006.346233