Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices

K.  Nomura; K.  Abe; S. Fujita; A.  Detion

1st International ICST Conference on Nano-Networks

Research Article

Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices

Cite: BibTeX Plain Text

@INPROCEEDINGS{10.1109/NANONET.2006.346226,
    author={K.  Nomura and K.  Abe and S. Fujita and A.  Detion},
    title={Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices},
    proceedings={1st International ICST Conference on Nano-Networks},
    publisher={IEEE},
    proceedings_a={NANO-NET},
    year={2007},
    month={4},
    keywords={},
    doi={10.1109/NANONET.2006.346226}
}

K. Nomura
K. Abe
S. Fujita
A. Detion
Year: 2007
Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices
NANO-NET
IEEE
DOI: 10.1109/NANONET.2006.346226

K. Nomura¹, K. Abe¹, S. Fujita¹, A. Detion¹

1: Corporate R&D Center, Toshiba Corp.,, Kawasaki

Abstract

The authors present a novel 3D crossbar for future network-on-a-chip implementations. They introduce a routing algorithm for the 3D crossbar circuit and detail two specific 3D crossbar topologies. They evaluate the defect tolerance of the 3D crossbar and quantify the number of extra layers required to support arbitrary permutations as a function of the defect rate. Further, we estimate the circuit performance and advantages of the 3D crossbar circuit based on post-silicon devices

Published: 2007-04-16
Publisher: IEEE

: http://dx.doi.org/10.1109/NANONET.2006.346226