A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

I.  Miro Panades; A.  Sheibanyrad; A.  Greiner

1st International ICST Conference on Nano-Networks

Research Article

A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

Cite: BibTeX Plain Text

@INPROCEEDINGS{10.1109/NANONET.2006.346219,
    author={ I.  Miro Panades and A.  Sheibanyrad and A.  Greiner},
    title={A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach},
    proceedings={1st International ICST Conference on Nano-Networks},
    publisher={IEEE},
    proceedings_a={NANO-NET},
    year={2007},
    month={4},
    keywords={},
    doi={10.1109/NANONET.2006.346219}
}

I. Miro Panades
A. Sheibanyrad
A. Greiner
Year: 2007
A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach
NANO-NET
IEEE
DOI: 10.1109/NANONET.2006.346219

I. Miro Panades¹, A. Sheibanyrad¹, A. Greiner¹

1: STMicroelcctronics, Grenoble

Abstract

The paper presents the DSPIN micro-network, that is an evolution of the SPIN architecture. DSPIN is a scalable packet switching micro-network dedicated to GALS (globally asynchronous, locally synchronous) clustered, multi-processors, systems on chip. The DSPIN architecture has a very small footprint and provides to the system designer both guaranteed latency, and guaranteed throughput services for real-time applications

Published: 2007-04-16
Publisher: IEEE

: http://dx.doi.org/10.1109/NANONET.2006.346219