Memory Efficient Block-Serial Architecture for Programmable, Multi-Rate Multi-Length LDPC Decoder

Xiyu Zhou; Zhaoyang Zhang

2nd International ICST Conference on Communications and Networking in China

Research Article

Memory Efficient Block-Serial Architecture for Programmable, Multi-Rate Multi-Length LDPC Decoder

Cite: BibTeX Plain Text

@INPROCEEDINGS{10.1109/CHINACOM.2007.4469593,
    author={Xiyu Zhou and Zhaoyang Zhang},
    title={Memory Efficient Block-Serial Architecture for Programmable, Multi-Rate Multi-Length LDPC Decoder},
    proceedings={2nd International ICST Conference on Communications and Networking in China},
    publisher={IEEE},
    proceedings_a={CHINACOM},
    year={2008},
    month={3},
    keywords={A-Min  Block-Serial  IEEE802.16e  LDPC  Memory Efficient  Multi-Length  Multi-Rate  Programmable},
    doi={10.1109/CHINACOM.2007.4469593}
}

Xiyu Zhou
Zhaoyang Zhang
Year: 2008
Memory Efficient Block-Serial Architecture for Programmable, Multi-Rate Multi-Length LDPC Decoder
CHINACOM
IEEE
DOI: 10.1109/CHINACOM.2007.4469593

Xiyu Zhou¹^,*, Zhaoyang Zhang¹^,*

1: Department of Information Science & Electronics Engineering, Zhejiang University, Hangzhou, China 310027

*Contact email: bymysea@gmail.com, ning_ming@zju.edu.cn

Abstract

This paper presents a flexible decoder architecture which supports twelve combinations of code lengths-576, 1152, 1728, 2304 bits and code rates-1/2, 2/3, 3/4 for block-serial irregular LDPC codes based on the IEEE 802.16e standard [1]. Approximate-Min Scheme is used to increase memory efficiency during message processing. At least 68.4% extrinsic message memory is saved and this reduction increases with the code rate. A prototype of the LDPC decoder has been implemented and tested on an Ateral FPGA.

Keywords: A-Min Block-Serial IEEE802.16e LDPC Memory Efficient Multi-Length Multi-Rate Programmable

Published: 2008-03-07
Publisher: IEEE
Modified: 2011-07-17

: http://dx.doi.org/10.1109/CHINACOM.2007.4469593