Cognitive Radio Oriented Wireless Networks. 12th International Conference, CROWNCOM 2017, Lisbon, Portugal, September 20-21, 2017, Proceedings

Research Article

Radio Hardware Virtualization for Coping with Dynamic Heterogeneous Wireless Environments

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  • @INPROCEEDINGS{10.1007/978-3-319-76207-4_24,
        author={Xianjun Jiao and Ingrid Moerman and Wei Liu and Felipe Figueiredo},
        title={Radio Hardware Virtualization for Coping with Dynamic Heterogeneous Wireless Environments},
        proceedings={Cognitive Radio Oriented Wireless Networks. 12th International Conference, CROWNCOM 2017, Lisbon, Portugal, September 20-21, 2017, Proceedings},
        proceedings_a={CROWNCOM},
        year={2018},
        month={3},
        keywords={Coexistence SDR Resource slicing FPGA C-RAN Virtualization CPRI},
        doi={10.1007/978-3-319-76207-4_24}
    }
    
  • Xianjun Jiao
    Ingrid Moerman
    Wei Liu
    Felipe Figueiredo
    Year: 2018
    Radio Hardware Virtualization for Coping with Dynamic Heterogeneous Wireless Environments
    CROWNCOM
    Springer
    DOI: 10.1007/978-3-319-76207-4_24
Xianjun Jiao1,*, Ingrid Moerman1,*, Wei Liu1,*, Felipe Figueiredo1,*
  • 1: Ghent University - imec
*Contact email: xianjun.jiao@ugent.be, ingrid.moerman@ugent.be, wei.liu@ugent.be, felipe.pereira@ugent.be

Abstract

Diverse wireless standards, designed for diverse traffic types, operate in the same wireless environment without coordination, often leading to interference and inefficient spectrum usage. Although C-RAN (Cloud/centralized RAN) is a promising architecture to achieve intra-operator network coordination, the architecture encounters challenge when low latency services and diverse access technologies are expected over non-fiber fronthaul. So, multi-standard multi-channel access point with low processing latency is preferred to be at the edge of network instead of central cloud. But, developing this kind of equipment is difficult as multiple radio chips and drivers have to be integrated and coordinated. In ORCA (Orchestration and Reconfiguration Control Architecture) project, a SDR architecture is developed on a single chip radio platform including hardware accelerators wrapped by unified software APIs, which offer the following capabilities: (1) concurrent data transmission over multiple virtual radios; (2) runtime composition and parametric control of radios; and (3) radio resource slicing, supporting independent operation of multiple standards in different bands, time slots or beams. Such an architecture offers a fast development cycle, as only software programming is required for creating and manipulating multiple radios. The architecture further achieves an efficient utilization of hardware resources, as accelerators can be shared by multiple virtual radios.