Research Article
FPGA-Based Turbo Decoder Hardware Accelerator in Cloud Radio Access Network (C-RAN)
@INPROCEEDINGS{10.1007/978-3-319-66625-9_21, author={Shaoxian Tang and Zhifeng Zhang and Jun Wu and Hui Zhu}, title={FPGA-Based Turbo Decoder Hardware Accelerator in Cloud Radio Access Network (C-RAN)}, proceedings={Communications and Networking. 11th EAI International Conference, ChinaCom 2016, Chongqing, China, September 24-26, 2016, Proceedings, Part I}, proceedings_a={CHINACOM}, year={2017}, month={10}, keywords={C-RAN SDR Xen FPGA Hardware accelerator Turbo decoder}, doi={10.1007/978-3-319-66625-9_21} }- Shaoxian Tang
Zhifeng Zhang
Jun Wu
Hui Zhu
Year: 2017
FPGA-Based Turbo Decoder Hardware Accelerator in Cloud Radio Access Network (C-RAN)
CHINACOM
Springer
DOI: 10.1007/978-3-319-66625-9_21
Abstract
In the Cloud Radio Access Network (C-RAN), the Software Defined Radio (SDR) is combined with multi-mode base stations (BSs) together. A lot of BSs are centralized in a Cloud center, the centralized BSs need high bandwidth and cost-effective resource allocation. Since BSs may also run on the virtualized machines, the hardware accelerator can provide faster signal processing speed. This paper uses the Xen virtualization to set up a C-RAN platform, where the SDR and the FPGA hardware connected with PCIe interface to server as the signal processing hardware accelerator. Experimental results demonstrate the turbo decoder accelerator based on the FPGA and Xen platform has good performance to support the SDR signal processing with high bandwidth. The turbo decoder hardware accelerator solved the timing constraints in C-RAN.