Cognitive Radio Oriented Wireless Networks. 13th EAI International Conference, CROWNCOM 2018, Ghent, Belgium, September 18–20, 2018, Proceedings

Research Article

High-Level and Compact Design of Cross-Channel LTE DownLink Channel Encoder

  • @INPROCEEDINGS{10.1007/978-3-030-05490-8_2,
        author={Jieming Xu and Miriam Leeser},
        title={High-Level and Compact Design of Cross-Channel LTE DownLink Channel Encoder},
        proceedings={Cognitive Radio Oriented Wireless Networks. 13th EAI International Conference, CROWNCOM 2018, Ghent, Belgium, September 18--20, 2018, Proceedings},
        proceedings_a={CROWNCOM},
        year={2019},
        month={1},
        keywords={LTE DL-SCH Reconfigurable hardware SDR},
        doi={10.1007/978-3-030-05490-8_2}
    }
    
  • Jieming Xu
    Miriam Leeser
    Year: 2019
    High-Level and Compact Design of Cross-Channel LTE DownLink Channel Encoder
    CROWNCOM
    Springer
    DOI: 10.1007/978-3-030-05490-8_2
Jieming Xu1,*, Miriam Leeser1,*
  • 1: Northeastern University
*Contact email: xu.jiem@husky.neu.edu, mel@coe.neu.edu

Abstract

Field Programmable Gate Arrays (FPGAs) provide great flexibility and speed in Software Defined Radio (SDR). However, as a mobile wireless protocol, the LTE system needs to maintain coding procedures for different channels, and the hardware’s implementation is more complex than other wireless local area network (WLAN) specifications. Thus a compact and resource reusable LTE channel coder is needed as hardware resources and speed are the main pain points in SDR implementation. Traditional FPGA design and synthesis only focus on low levels of resource reuse, and IPs are independently designed without considering the whole system, which causes resource waste. In this paper, we describe a LTE downlink channel encoder processing chain implemented in FPGA hardware. Reuse in the whole system is done at a channel level and above, and scarce resources like BRAM are shared between processing units to maximize reuse. The system can efficiently process data and control channel signals at the same time using the same hardware. For the data channel, we use cross-component optimization to reduce the usage of BRAMs up to 25% for high volume data buffering. A novel rate matching design reduces the latency which improves the performance. By applying high-level reuse, the cross-component design can reduce resource usage while maintaining a good processing speed.